Lines Matching refs:ep
128 struct xilly_endpoint *ep = data; in xillybus_isr() local
136 buf = ep->msgbuf_addr; in xillybus_isr()
137 buf_size = ep->msg_buf_size/sizeof(u32); in xillybus_isr()
139 ep->ephw->hw_sync_sgl_for_cpu(ep, in xillybus_isr()
140 ep->msgbuf_dma_addr, in xillybus_isr()
141 ep->msg_buf_size, in xillybus_isr()
145 if (((buf[i+1] >> 28) & 0xf) != ep->msg_counter) { in xillybus_isr()
146 malformed_message(ep, &buf[i]); in xillybus_isr()
147 dev_warn(ep->dev, in xillybus_isr()
150 ep->msg_counter, in xillybus_isr()
153 if (++ep->failed_messages > 10) { in xillybus_isr()
154 dev_err(ep->dev, in xillybus_isr()
157 ep->ephw->hw_sync_sgl_for_device( in xillybus_isr()
158 ep, in xillybus_isr()
159 ep->msgbuf_dma_addr, in xillybus_isr()
160 ep->msg_buf_size, in xillybus_isr()
164 ep->registers + fpga_msg_ctrl_reg); in xillybus_isr()
172 dev_err(ep->dev, "Bad interrupt message. Stopping.\n"); in xillybus_isr()
188 if ((msg_channel > ep->num_channels) || in xillybus_isr()
190 malformed_message(ep, &buf[i]); in xillybus_isr()
194 channel = ep->channels[msg_channel]; in xillybus_isr()
198 malformed_message(ep, &buf[i]); in xillybus_isr()
215 malformed_message(ep, &buf[i]); in xillybus_isr()
234 if ((msg_channel > ep->num_channels) || in xillybus_isr()
236 !ep->channels[msg_channel]->wr_supports_nonempty) { in xillybus_isr()
237 malformed_message(ep, &buf[i]); in xillybus_isr()
241 channel = ep->channels[msg_channel]; in xillybus_isr()
244 malformed_message(ep, &buf[i]); in xillybus_isr()
256 ep->idtlen = msg_data; in xillybus_isr()
257 wake_up_interruptible(&ep->ep_wait); in xillybus_isr()
261 if ((msg_channel > ep->num_channels) || in xillybus_isr()
263 !ep->channels[msg_channel]->num_wr_buffers) { in xillybus_isr()
264 malformed_message(ep, &buf[i]); in xillybus_isr()
267 channel = ep->channels[msg_channel]; in xillybus_isr()
281 ep->fatal_error = 1; in xillybus_isr()
282 wake_up_interruptible(&ep->ep_wait); /* For select() */ in xillybus_isr()
283 dev_err(ep->dev, in xillybus_isr()
287 malformed_message(ep, &buf[i]); in xillybus_isr()
292 ep->ephw->hw_sync_sgl_for_device(ep, in xillybus_isr()
293 ep->msgbuf_dma_addr, in xillybus_isr()
294 ep->msg_buf_size, in xillybus_isr()
297 ep->msg_counter = (ep->msg_counter + 1) & 0xf; in xillybus_isr()
298 ep->failed_messages = 0; in xillybus_isr()
299 iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */ in xillybus_isr()
321 static int xilly_get_dma_buffers(struct xilly_endpoint *ep, in xilly_get_dma_buffers() argument
328 struct device *dev = ep->dev; in xilly_get_dma_buffers()
347 dev_err(ep->dev, in xilly_get_dma_buffers()
372 rc = ep->ephw->map_single(ep, s->salami, in xilly_get_dma_buffers()
379 ep->registers + fpga_dma_bufaddr_lowaddr_reg); in xilly_get_dma_buffers()
381 ep->registers + fpga_dma_bufaddr_highaddr_reg); in xilly_get_dma_buffers()
389 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
391 ep->msgbuf_addr = s->salami; in xilly_get_dma_buffers()
392 ep->msgbuf_dma_addr = dma_addr; in xilly_get_dma_buffers()
393 ep->msg_buf_size = bytebufsize; in xilly_get_dma_buffers()
396 ep->registers + fpga_dma_bufno_reg); in xilly_get_dma_buffers()
405 static int xilly_setupchannels(struct xilly_endpoint *ep, in xilly_setupchannels() argument
409 struct device *dev = ep->dev; in xilly_setupchannels()
434 channel = devm_kcalloc(dev, ep->num_channels, in xilly_setupchannels()
439 ep->channels = devm_kcalloc(dev, ep->num_channels + 1, in xilly_setupchannels()
442 if (!ep->channels) in xilly_setupchannels()
445 ep->channels[0] = NULL; /* Channel 0 is message buf. */ in xilly_setupchannels()
449 for (i = 1; i <= ep->num_channels; i++) { in xilly_setupchannels()
477 channel->endpoint = ep; in xilly_setupchannels()
482 ep->channels[i] = channel++; in xilly_setupchannels()
499 if ((channelnum > ep->num_channels) || in xilly_setupchannels()
501 dev_err(ep->dev, in xilly_setupchannels()
506 channel = ep->channels[channelnum]; /* NULL for msg channel */ in xilly_setupchannels()
533 rc = xilly_get_dma_buffers(ep, &rd_alloc, buffers, in xilly_setupchannels()
547 rc = xilly_get_dma_buffers(ep, &wr_alloc, buffers, in xilly_setupchannels()
550 rc = xilly_get_dma_buffers(ep, &wr_alloc, NULL, in xilly_setupchannels()
560 dev_err(ep->dev, in xilly_setupchannels()