Lines Matching refs:OWL_DIVIDER_HW
221 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
227 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
257 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
281 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
287 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
293 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
299 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
305 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
311 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
317 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
323 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
329 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
335 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
341 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
347 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
353 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
371 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
377 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
383 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
394 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
403 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),