Lines Matching refs:OWL_DIVIDER_HW
247 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
253 OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
275 OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
305 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
335 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
341 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
353 OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
359 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
365 OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
370 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
375 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
386 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
391 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
396 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
401 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
431 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
437 OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
443 OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
449 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
455 OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
461 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
467 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
473 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
479 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
485 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),