82 	u32 md;  member
114 	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,  in davinci_lpsc_config()
118 		regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,  in davinci_lpsc_config()
140 	regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,  in davinci_lpsc_config()
166 	regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);  in davinci_lpsc_clk_is_enabled()
236 			  u32 md, u32 pd, u32 flags)  in davinci_lpsc_clk_register()  argument
262 	lpsc->md = md;  in davinci_lpsc_clk_register()
301 	regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);  in davinci_lpsc_clk_reset()
368 	return lpsc->md;  in davinci_psc_reset_of_xlate()
428 						 regmap, info->md, info->pd,  in __davinci_psc_register_clocks()
436 		clks[info->md] = lpsc->hw.clk;  in __davinci_psc_register_clocks()
437 		pm_domains[info->md] = &lpsc->pm_domain;  in __davinci_psc_register_clocks()
484 		struct clk *clk = psc->clk_data.clks[info->md];  in davinci_psc_register_clocks()