clk/mediatek/clk-mt2701.c

817 #define GATE_PERI0(_id, _name, _parent, _shift) {	\  macro
836 	GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
837 	GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
838 	GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
839 	GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
840 	GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
841 	GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
842 	GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
843 	GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
844 	GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
845 	GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
846 	GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
847 	GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
848 	GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
849 	GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
850 	GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
851 	GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
852 	GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
853 	GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
854 	GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
855 	GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
856 	GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
857 	GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
858 	GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
859 	GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
860 	GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
861 	GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
862 	GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
863 	GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
864 	GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
865 	GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
866 	GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
867 	GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),