clk/mediatek/clk-mt8135.c

448 #define GATE_PERI0(_id, _name, _parent, _shift) {	\  macro
468 	GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
469 	GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
470 	GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
471 	GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
472 	GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
473 	GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
474 	GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
475 	GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
476 	GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
477 	GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
478 	GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
479 	GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
480 	GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
481 	GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
482 	GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
483 	GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
484 	GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
485 	GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
486 	GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
487 	GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
488 	GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
489 	GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
490 	GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
491 	GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
492 	GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
493 	GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
494 	GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
495 	GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
496 	GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
497 	GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
498 	GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
499 	GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),