216 	clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);  in mx28_clocks_init()
217 	clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);  in mx28_clocks_init()
218 	clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);  in mx28_clocks_init()
219 	clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);  in mx28_clocks_init()
220 	clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);  in mx28_clocks_init()
221 	clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);  in mx28_clocks_init()
222 	clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);  in mx28_clocks_init()
223 	clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);  in mx28_clocks_init()
224 	clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);  in mx28_clocks_init()
225 	clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);  in mx28_clocks_init()
226 	clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);  in mx28_clocks_init()
227 	clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);  in mx28_clocks_init()
228 	clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);  in mx28_clocks_init()
229 	clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);  in mx28_clocks_init()
230 	clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);  in mx28_clocks_init()
231 	clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);  in mx28_clocks_init()
232 	clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);  in mx28_clocks_init()
233 	clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);  in mx28_clocks_init()
234 	clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);  in mx28_clocks_init()