Lines Matching refs:GATE
22 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
23 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
24 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
25 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
26 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
27 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
28 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
29 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
30 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
31 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
32 GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
33 GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
34 GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
35 GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
36 GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
37 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
38 GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
39 GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
40 GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
41 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
42 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
43 GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
44 GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
46 GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
47 GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
48 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
49 GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
50 GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
51 GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
208 GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
209 GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
210 GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
211 GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
212 GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",
214 GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",
216 GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
217 GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
218 GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
219 GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
220 GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
221 GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
222 GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
223 GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
278 GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
279 GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
280 GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
281 GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
282 GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
283 GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
284 GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
285 GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
286 GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
287 GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
288 GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
289 GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
290 GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
291 GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
292 GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
293 GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
294 GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
295 GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
296 GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
297 GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
298 GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
299 GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
300 GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
320 GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
321 GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)