431 	u32 l, low, high, ctl;  in clk_alpha_pll_recalc_rate()  local
438 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);  in clk_alpha_pll_recalc_rate()
439 	if (ctl & PLL_ALPHA_EN) {  in clk_alpha_pll_recalc_rate()
632 	u32 l, alpha = 0, ctl, alpha_m, alpha_n;  in alpha_pll_huayra_recalc_rate()  local
635 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);  in alpha_pll_huayra_recalc_rate()
637 	if (ctl & PLL_ALPHA_EN) {  in alpha_pll_huayra_recalc_rate()
656 		if (!(ctl & PLL_ALPHA_MODE))  in alpha_pll_huayra_recalc_rate()
685 	u32 l, a, ctl, cur_alpha = 0;  in alpha_pll_huayra_set_rate()  local
689 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);  in alpha_pll_huayra_set_rate()
691 	if (ctl & PLL_ALPHA_EN)  in alpha_pll_huayra_set_rate()
766 	u32 ctl;  in clk_alpha_pll_postdiv_recalc_rate()  local
768 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);  in clk_alpha_pll_postdiv_recalc_rate()
770 	ctl >>= PLL_POST_DIV_SHIFT;  in clk_alpha_pll_postdiv_recalc_rate()
771 	ctl &= PLL_POST_DIV_MASK(pll);  in clk_alpha_pll_postdiv_recalc_rate()
773 	return parent_rate >> fls(ctl);  in clk_alpha_pll_postdiv_recalc_rate()
813 	u32 ctl, div;  in clk_alpha_pll_postdiv_round_ro_rate()  local
815 	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);  in clk_alpha_pll_postdiv_round_ro_rate()
817 	ctl >>= PLL_POST_DIV_SHIFT;  in clk_alpha_pll_postdiv_round_ro_rate()
818 	ctl &= BIT(pll->width) - 1;  in clk_alpha_pll_postdiv_round_ro_rate()
819 	div = 1 << fls(ctl);  in clk_alpha_pll_postdiv_round_ro_rate()