50 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_is_enabled()  local
54 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in clk_rcg2_is_enabled()
63 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_get_parent()  local
68 	ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_get_parent()
76 		if (cfg == rcg->parent_map[i].cfg)  in clk_rcg2_get_parent()
85 static int update_config(struct clk_rcg2 *rcg)  in update_config()  argument
89 	struct clk_hw *hw = &rcg->clkr.hw;  in update_config()
92 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in update_config()
99 		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);  in update_config()
113 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_parent()  local
115 	u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_rcg2_set_parent()
117 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_rcg2_set_parent()
122 	return update_config(rcg);  in clk_rcg2_set_parent()
153 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_recalc_rate()  local
156 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_recalc_rate()
158 	if (rcg->mnd_width) {  in clk_rcg2_recalc_rate()
159 		mask = BIT(rcg->mnd_width) - 1;  in clk_rcg2_recalc_rate()
160 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);  in clk_rcg2_recalc_rate()
162 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);  in clk_rcg2_recalc_rate()
170 	mask = BIT(rcg->hid_width) - 1;  in clk_rcg2_recalc_rate()
183 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in _freq_tbl_determine_rate()  local
200 	index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in _freq_tbl_determine_rate()
237 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_rate()  local
239 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);  in clk_rcg2_determine_rate()
245 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_determine_floor_rate()  local
247 	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);  in clk_rcg2_determine_floor_rate()
250 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in __clk_rcg2_configure()  argument
253 	struct clk_hw *hw = &rcg->clkr.hw;  in __clk_rcg2_configure()
254 	int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in __clk_rcg2_configure()
259 	if (rcg->mnd_width && f->n) {  in __clk_rcg2_configure()
260 		mask = BIT(rcg->mnd_width) - 1;  in __clk_rcg2_configure()
261 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
262 				rcg->cmd_rcgr + M_REG, mask, f->m);  in __clk_rcg2_configure()
266 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
267 				rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));  in __clk_rcg2_configure()
271 		ret = regmap_update_bits(rcg->clkr.regmap,  in __clk_rcg2_configure()
272 				rcg->cmd_rcgr + D_REG, mask, ~f->n);  in __clk_rcg2_configure()
277 	mask = BIT(rcg->hid_width) - 1;  in __clk_rcg2_configure()
280 	cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in __clk_rcg2_configure()
281 	if (rcg->mnd_width && f->n && (f->m != f->n))  in __clk_rcg2_configure()
284 	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in __clk_rcg2_configure()
288 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)  in clk_rcg2_configure()  argument
292 	ret = __clk_rcg2_configure(rcg, f);  in clk_rcg2_configure()
296 	return update_config(rcg);  in clk_rcg2_configure()
302 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in __clk_rcg2_set_rate()  local
307 		f = qcom_find_freq_floor(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
310 		f = qcom_find_freq(rcg->freq_tbl, rate);  in __clk_rcg2_set_rate()
319 	return clk_rcg2_configure(rcg, f);  in __clk_rcg2_set_rate()
398 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_set_rate()  local
399 	struct freq_tbl f = *rcg->freq_tbl;  in clk_edp_pixel_set_rate()
404 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_set_rate()
420 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_set_rate()
428 		return clk_rcg2_configure(rcg, &f);  in clk_edp_pixel_set_rate()
444 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_edp_pixel_determine_rate()  local
445 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_edp_pixel_determine_rate()
449 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_edp_pixel_determine_rate()
451 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_edp_pixel_determine_rate()
470 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_edp_pixel_determine_rate()
498 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_determine_rate()  local
499 	const struct freq_tbl *f = rcg->freq_tbl;  in clk_byte_determine_rate()
500 	int index = qcom_find_src_index(hw, rcg->parent_map, f->src);  in clk_byte_determine_rate()
502 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_determine_rate()
522 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte_set_rate()  local
523 	struct freq_tbl f = *rcg->freq_tbl;  in clk_byte_set_rate()
525 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte_set_rate()
532 	return clk_rcg2_configure(rcg, &f);  in clk_byte_set_rate()
556 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_determine_rate()  local
558 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_determine_rate()
579 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_byte2_set_rate()  local
583 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_byte2_set_rate()
591 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_byte2_set_rate()
596 		if (cfg == rcg->parent_map[i].cfg) {  in clk_byte2_set_rate()
597 			f.src = rcg->parent_map[i].src;  in clk_byte2_set_rate()
598 			return clk_rcg2_configure(rcg, &f);  in clk_byte2_set_rate()
658 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_pixel_set_rate()  local
663 	u32 mask = BIT(rcg->hid_width) - 1;  in clk_pixel_set_rate()
667 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_pixel_set_rate()
672 		if (cfg == rcg->parent_map[i].cfg) {  in clk_pixel_set_rate()
673 			f.src = rcg->parent_map[i].src;  in clk_pixel_set_rate()
684 		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_pixel_set_rate()
692 		return clk_rcg2_configure(rcg, &f);  in clk_pixel_set_rate()
766 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_gfx3d_set_rate_and_parent()  local
771 	cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;  in clk_gfx3d_set_rate_and_parent()
772 	ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);  in clk_gfx3d_set_rate_and_parent()
776 	return update_config(rcg);  in clk_gfx3d_set_rate_and_parent()
803 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_set_force_enable()  local
807 	ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_set_force_enable()
826 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_clear_force_enable()  local
828 	return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,  in clk_rcg2_clear_force_enable()
835 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_force_enable_clear()  local
842 	ret = clk_rcg2_configure(rcg, f);  in clk_rcg2_shared_force_enable_clear()
852 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_set_rate()  local
855 	f = qcom_find_freq(rcg->freq_tbl, rate);  in clk_rcg2_shared_set_rate()
864 		return __clk_rcg2_configure(rcg, f);  in clk_rcg2_shared_set_rate()
877 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_enable()  local
888 	ret = update_config(rcg);  in clk_rcg2_shared_enable()
897 	struct clk_rcg2 *rcg = to_clk_rcg2(hw);  in clk_rcg2_shared_disable()  local
904 	regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);  in clk_rcg2_shared_disable()
916 	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,  in clk_rcg2_shared_disable()
917 		     rcg->safe_src_index << CFG_SRC_SEL_SHIFT);  in clk_rcg2_shared_disable()
919 	update_config(rcg);  in clk_rcg2_shared_disable()
924 	regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);  in clk_rcg2_shared_disable()