41 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);  in rockchip_ddrclk_sip_set_rate()  local
45 	spin_lock_irqsave(ddrclk->lock, flags);  in rockchip_ddrclk_sip_set_rate()
49 	spin_unlock_irqrestore(ddrclk->lock, flags);  in rockchip_ddrclk_sip_set_rate()
82 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);  in rockchip_ddrclk_get_parent()  local
85 	val = clk_readl(ddrclk->reg_base +  in rockchip_ddrclk_get_parent()
86 			ddrclk->mux_offset) >> ddrclk->mux_shift;  in rockchip_ddrclk_get_parent()
87 	val &= GENMASK(ddrclk->mux_width - 1, 0);  in rockchip_ddrclk_get_parent()
107 	struct rockchip_ddrclk *ddrclk;  in rockchip_clk_register_ddrclk()  local
111 	ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);  in rockchip_clk_register_ddrclk()
112 	if (!ddrclk)  in rockchip_clk_register_ddrclk()
128 		kfree(ddrclk);  in rockchip_clk_register_ddrclk()
132 	ddrclk->reg_base = reg_base;  in rockchip_clk_register_ddrclk()
133 	ddrclk->lock = lock;  in rockchip_clk_register_ddrclk()
134 	ddrclk->hw.init = &init;  in rockchip_clk_register_ddrclk()
135 	ddrclk->mux_offset = mux_offset;  in rockchip_clk_register_ddrclk()
136 	ddrclk->mux_shift = mux_shift;  in rockchip_clk_register_ddrclk()
137 	ddrclk->mux_width = mux_width;  in rockchip_clk_register_ddrclk()
138 	ddrclk->div_shift = div_shift;  in rockchip_clk_register_ddrclk()
139 	ddrclk->div_width = div_width;  in rockchip_clk_register_ddrclk()
140 	ddrclk->ddr_flag = ddr_flag;  in rockchip_clk_register_ddrclk()
142 	clk = clk_register(NULL, &ddrclk->hw);  in rockchip_clk_register_ddrclk()
144 		kfree(ddrclk);  in rockchip_clk_register_ddrclk()