clk/rockchip/clk-rk3328.c

150 PNAME(mux_pll_p)		= { "xin24m" };
152 PNAME(mux_2plls_p)		= { "cpll", "gpll" };
153 PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
154 PNAME(mux_cpll_gpll_apll_p)	= { "cpll", "gpll", "apll" };
155 PNAME(mux_2plls_xin24m_p)	= { "cpll", "gpll", "xin24m" };
156 PNAME(mux_2plls_hdmiphy_p)	= { "cpll", "gpll",
158 PNAME(mux_4plls_p)		= { "cpll", "gpll",
161 PNAME(mux_2plls_u480m_p)	= { "cpll", "gpll",
163 PNAME(mux_2plls_24m_u480m_p)	= { "cpll", "gpll",
166 PNAME(mux_ddrphy_p)		= { "dpll", "apll", "cpll" };
167 PNAME(mux_armclk_p)		= { "apll_core",
171 PNAME(mux_hdmiphy_p)		= { "hdmi_phy", "xin24m" };
172 PNAME(mux_usb480m_p)		= { "usb480m_phy",
175 PNAME(mux_i2s0_p)		= { "clk_i2s0_div",
179 PNAME(mux_i2s1_p)		= { "clk_i2s1_div",
183 PNAME(mux_i2s2_p)		= { "clk_i2s2_div",
187 PNAME(mux_i2s1out_p)		= { "clk_i2s1", "xin12m"};
188 PNAME(mux_i2s2out_p)		= { "clk_i2s2", "xin12m" };
189 PNAME(mux_spdif_p)		= { "clk_spdif_div",
193 PNAME(mux_uart0_p)		= { "clk_uart0_div",
196 PNAME(mux_uart1_p)		= { "clk_uart1_div",
199 PNAME(mux_uart2_p)		= { "clk_uart2_div",
203 PNAME(mux_sclk_cif_p)		= { "clk_cif_src",
205 PNAME(mux_dclk_lcdc_p)		= { "hdmiphy",
207 PNAME(mux_aclk_peri_pre_p)	= { "cpll_peri",
210 PNAME(mux_ref_usb3otg_src_p)	= { "xin24m",
212 PNAME(mux_xin24m_32k_p)		= { "xin24m",
214 PNAME(mux_mac2io_src_p)		= { "clk_mac2io_src",
216 PNAME(mux_mac2phy_src_p)	= { "clk_mac2phy_src",
218 PNAME(mux_mac2io_ext_p)		= { "clk_mac2io",