Lines Matching refs:GATE
209 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
211 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
213 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
221 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
223 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
235 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
237 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
239 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED,
241 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED,
260 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
262 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
264 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
266 GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0,
268 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,
270 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,
272 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,
279 GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
281 GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
283 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0,
285 GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
287 GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
289 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0,
291 GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0,
299 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
317 GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
319 GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED,
322 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0,
324 GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0,
329 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0,
331 GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0,
336 GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0,
338 GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0,
343 GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0,
345 GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0,
350 GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED,
357 GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
359 GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
361 GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
363 GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED,
365 GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED,
379 GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED,
381 GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
383 GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
385 GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED,
387 GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED,
395 GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
397 GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
399 GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
401 GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
403 GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED,
405 GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED,
407 GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED,
416 GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0,
421 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
426 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
431 GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0,
436 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
438 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
440 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
442 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
452 GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0,
454 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
456 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0,
458 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
461 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0,
463 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
474 GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0,
480 GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0,
482 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0,
485 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0,
487 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
493 GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED,
495 GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
497 GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
499 GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED,
516 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
529 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
539 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
543 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
545 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
547 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
557 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
559 GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
561 GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
563 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
565 GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED,
567 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
570 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0,
572 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0,
574 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0,
577 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0,
579 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0,
588 GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0,
613 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0,
615 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0,
617 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0,
629 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0,
631 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0,
633 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0,
638 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
640 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
642 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0,
644 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0,
646 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0,
649 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
651 GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0,
653 GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0,
655 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0,
660 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0,
666 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
668 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
670 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
674 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
676 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
678 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
684 GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED,
686 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
688 GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
690 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
692 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
694 GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
696 GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED,
707 GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
712 GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
715 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
717 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
738 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
739 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
740 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
745 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
747 GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS),
748 GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS),
749 GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS),
750 GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS),
751 GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS),
756 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
763 GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
764 GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
765 GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_mac", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
766 GATE(ACLK_GMAC, "aclk_gmac", "aclk_periph", 0, RV1108_CLKGATE_CON(15), 4, GFLAGS),
767 GATE(PCLK_GMAC, "pclk_gmac", "pclk_periph", 0, RV1108_CLKGATE_CON(15), 5, GFLAGS),