Lines Matching refs:GATE
442 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
444 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
446 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
448 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
452 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
454 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
456 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
458 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
460 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
462 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
466 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
468 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
470 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
472 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
474 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
476 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
478 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
479 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
480 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
481 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
482 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
484 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
486 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
488 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
490 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
492 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
494 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
496 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
498 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
500 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
502 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
504 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
508 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
510 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
512 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
514 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
518 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
522 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
526 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
528 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
530 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
534 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
536 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
538 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
540 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
544 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
545 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
547 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
549 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
551 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
553 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
557 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
559 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
561 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
563 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
566 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
568 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
570 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
574 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
576 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
578 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
580 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
582 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
584 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
586 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
588 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
590 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
592 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
594 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
596 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
597 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
599 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
600 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
603 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
605 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
607 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
608 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
611 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
612 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
614 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
616 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
619 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
621 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
623 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
625 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
626 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
627 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
628 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
631 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
632 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
634 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
636 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
640 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
641 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
643 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
644 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
645 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
646 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
647 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
648 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
649 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
650 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
653 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
654 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
655 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
656 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
657 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
658 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
659 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
660 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
661 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
662 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
663 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
664 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
665 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
666 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
667 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
668 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
980 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
982 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
984 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
986 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
988 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
990 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
992 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
994 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
996 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
998 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
1000 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
1002 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
1004 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
1006 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
1008 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
1010 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
1012 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
1014 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
1016 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
1018 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
1020 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
1022 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
1024 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
1026 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
1028 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
1030 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1032 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1034 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1038 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
1040 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1042 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1044 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1046 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1048 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1050 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1052 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1054 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1056 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1058 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1062 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",