Lines Matching refs:GATE
169 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
170 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
171 GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
172 GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
173 GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
175 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
177 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
179 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
182 GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
183 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
184 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
185 GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
186 GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
188 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
190 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
192 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
194 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
197 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
200 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
201 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
202 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
203 GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
204 GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
205 GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
206 GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
207 GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
208 GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
209 GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
210 GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
211 GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
212 GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
214 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
216 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
218 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
220 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
223 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
224 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
225 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),