36 	unsigned short regofs;  /* register offset */  member
44 	unsigned short regofs;  /* register offset */  member
79 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -  in pll_clk_recalc_rate()
87 		u32 cfg0 = clkc_readl(clk->regofs);  in pll_clk_recalc_rate()
151 	clkc_writel(reg, clk->regofs);  in pll_clk_set_rate()
153 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
156 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
219 	.regofs = SIRFSOC_CLKC_PLL1_CFG0,
226 	.regofs = SIRFSOC_CLKC_PLL2_CFG0,
233 	.regofs = SIRFSOC_CLKC_PLL3_CFG0,
300 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_get_parent()
315 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_set_parent()
323 	clkc_writel(cfg | parent, clk->regofs);  in dmn_clk_set_parent()
325 	while (clkc_readl(clk->regofs) & BIT(3))  in dmn_clk_set_parent()
338 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_recalc_rate()
396 	reg = clkc_readl(clk->regofs);  in dmn_clk_set_rate()
399 	clkc_writel(reg, clk->regofs);  in dmn_clk_set_rate()
402 	while (clkc_readl(clk->regofs) & BIT(25))  in dmn_clk_set_rate()
460 	.regofs = SIRFSOC_CLKC_MEM_CFG,
475 	.regofs = SIRFSOC_CLKC_SYS_CFG,
489 	.regofs = SIRFSOC_CLKC_IO_CFG,
512 	.regofs = SIRFSOC_CLKC_CPU_CFG,
539 	.regofs = SIRFSOC_CLKC_DSP_CFG,
554 	.regofs = SIRFSOC_CLKC_GFX_CFG,
569 	.regofs = SIRFSOC_CLKC_MM_CFG,
589 	.regofs = SIRFSOC_CLKC_LCD_CFG,
604 	.regofs = SIRFSOC_CLKC_LCD_CFG,