Lines Matching defs:socfpga_gate_clk

52 struct socfpga_gate_clk {  struct
53 	struct clk_gate hw;
54 	char *parent_name;
55 	u32 fixed_div;
56 	void __iomem *div_reg;
57 	void __iomem *bypass_reg;
58 	struct regmap *sys_mgr_base_addr;
59 	u32 width;	/* only valid if div_reg != 0 */
60 	u32 shift;	/* only valid if div_reg != 0 */
61 	u32 bypass_shift;      /* only valid if bypass_reg != 0 */
62 	u32 clk_phase[2];