Lines Matching refs:divn_shift
264 #define divn_shift(p) (p)->params->div_nmp->divn_shift macro
268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
279 .divn_shift = PLL_BASE_DIVN_SHIFT,
677 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
708 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
970 val |= sel.n << divn_shift(pll); in clk_plle_enable()
1004 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1606 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1874 .divn_shift = PLLE_BASE_DIVN_SHIFT,
2068 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2424 val |= sel.n << divn_shift(pll); in clk_plle_tegra210_enable()