Lines Matching refs:pll_params
1159 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, in _pll_fixed_mdiv() argument
1162 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1164 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1165 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1166 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1168 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1169 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1171 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1224 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, in _setup_dynamic_ramp() argument
1253 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1254 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1255 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1801 void __iomem *pmc, struct tegra_clk_pll_params *pll_params, in _tegra_init_pll() argument
1813 pll->params = pll_params; in _tegra_init_pll()
1816 if (!pll_params->div_nmp) in _tegra_init_pll()
1817 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1853 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pll() argument
1859 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1861 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pll()
1884 unsigned long flags, struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle() argument
1890 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1892 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1893 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1895 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_plle()
1909 struct tegra_clk_pll_params *pll_params, spinlock_t *lock) in tegra_clk_register_pllu() argument
1914 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
1916 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu()
1976 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllxc() argument
1991 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
1996 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
1998 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
1999 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2006 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2009 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate); in tegra_clk_register_pllxc()
2013 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2014 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2017 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2019 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2021 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2025 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllxc()
2040 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre() argument
2047 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2049 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2050 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2053 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre()
2061 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2062 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2066 m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllre()
2068 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2089 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllm() argument
2096 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2108 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2110 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2111 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2114 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2115 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2116 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllm()
2131 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc() argument
2135 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2152 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2154 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2155 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc()
2168 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllc()
2169 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2188 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2189 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2190 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2205 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra114() argument
2212 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra114()
2219 val_aux = pll_readl(pll_params->aux_reg, pll); in tegra_clk_register_plle_tegra114()
2229 pll_writel(val_aux, pll_params->aux_reg, pll); in tegra_clk_register_plle_tegra114()
2243 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllu_tegra114() argument
2249 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2251 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllu_tegra114()
2276 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss() argument
2286 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2296 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss()
2306 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2310 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); in tegra_clk_register_pllss()
2311 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2313 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2320 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2325 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2326 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2327 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2330 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2332 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2338 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2339 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2359 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllre_tegra210() argument
2365 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2367 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2368 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2371 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllre_tegra210()
2521 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_plle_tegra210() argument
2528 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_plle_tegra210()
2535 val_aux = pll_readl(pll_params->aux_reg, pll); in tegra_clk_register_plle_tegra210()
2545 pll_writel(val_aux, pll_params->aux_reg, pll); in tegra_clk_register_plle_tegra210()
2559 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllc_tegra210() argument
2563 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2579 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2581 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2582 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2585 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2586 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllc_tegra210()
2601 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllss_tegra210() argument
2609 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2619 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2627 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2629 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2630 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2633 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2634 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock); in tegra_clk_register_pllss_tegra210()
2650 struct tegra_clk_pll_params *pll_params, in tegra_clk_register_pllmb() argument
2657 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2669 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2671 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2672 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2675 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2676 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()
2677 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); in tegra_clk_register_pllmb()