241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)  macro
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
363 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_enable()
370 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_enable()
408 		val = pll_readl(pll->params->reset_reg, pll);  in _clk_pll_disable()
414 		val = pll_readl(pll->params->iddq_reg, pll);  in _clk_pll_disable()
424 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
434 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1582 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1597 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1617 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1634 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1642 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1653 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1661 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
2219 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2398 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2415 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2438 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2454 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2479 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2487 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2535 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()