248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)  macro
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
365 		pll_writel(val, pll->params->iddq_reg, pll);  in _clk_pll_enable()
372 		pll_writel(val, pll->params->reset_reg, pll);  in _clk_pll_enable()
410 		pll_writel(val, pll->params->reset_reg, pll);  in _clk_pll_disable()
416 		pll_writel(val, pll->params->iddq_reg, pll);  in _clk_pll_disable()
427 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);  in pll_clk_start_ss()
437 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);  in pll_clk_stop_ss()
1585 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1599 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1621 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1623 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1626 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1637 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1640 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1647 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1650 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1657 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1663 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
2188 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
2189 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
2190 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
2229 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
2325 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
2326 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
2327 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
2417 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2442 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2444 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2447 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra210_enable()
2457 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2460 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_enable()
2489 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra210_disable()
2545 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra210()