42 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_get_parent()  local
49 	val = readl_relaxed(sdmmc_mux->reg);  in clk_sdmmc_mux_get_parent()
68 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_set_parent()  local
72 	val = readl_relaxed(sdmmc_mux->reg);  in clk_sdmmc_mux_set_parent()
81 	writel(val, sdmmc_mux->reg);  in clk_sdmmc_mux_set_parent()
89 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_recalc_rate()  local
94 	val = readl_relaxed(sdmmc_mux->reg);  in clk_sdmmc_mux_recalc_rate()
109 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_determine_rate()  local
119 	div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);  in clk_sdmmc_mux_determine_rate()
123 	if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)  in clk_sdmmc_mux_determine_rate()
135 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_set_rate()  local
141 	div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);  in clk_sdmmc_mux_set_rate()
145 	if (sdmmc_mux->lock)  in clk_sdmmc_mux_set_rate()
146 		spin_lock_irqsave(sdmmc_mux->lock, flags);  in clk_sdmmc_mux_set_rate()
156 	writel(val, sdmmc_mux->reg);  in clk_sdmmc_mux_set_rate()
157 	fence_udelay(2, sdmmc_mux->reg);  in clk_sdmmc_mux_set_rate()
159 	if (sdmmc_mux->lock)  in clk_sdmmc_mux_set_rate()
160 		spin_unlock_irqrestore(sdmmc_mux->lock, flags);  in clk_sdmmc_mux_set_rate()
167 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_is_enabled()  local
168 	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;  in clk_sdmmc_mux_is_enabled()
169 	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;  in clk_sdmmc_mux_is_enabled()
178 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_enable()  local
179 	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;  in clk_sdmmc_mux_enable()
180 	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;  in clk_sdmmc_mux_enable()
189 	struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);  in clk_sdmmc_mux_disable()  local
190 	const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;  in clk_sdmmc_mux_disable()
191 	struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;  in clk_sdmmc_mux_disable()
214 	struct tegra_sdmmc_mux *sdmmc_mux;  in tegra_clk_register_sdmmc_mux_div()  local
226 	sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);  in tegra_clk_register_sdmmc_mux_div()
227 	if (!sdmmc_mux)  in tegra_clk_register_sdmmc_mux_div()
231 	sdmmc_mux->hw.init = &init;  in tegra_clk_register_sdmmc_mux_div()
232 	sdmmc_mux->reg = clk_base + offset;  in tegra_clk_register_sdmmc_mux_div()
233 	sdmmc_mux->lock = lock;  in tegra_clk_register_sdmmc_mux_div()
234 	sdmmc_mux->gate.clk_base = clk_base;  in tegra_clk_register_sdmmc_mux_div()
235 	sdmmc_mux->gate.regs = bank;  in tegra_clk_register_sdmmc_mux_div()
236 	sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;  in tegra_clk_register_sdmmc_mux_div()
237 	sdmmc_mux->gate.clk_num = clk_num;  in tegra_clk_register_sdmmc_mux_div()
238 	sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;  in tegra_clk_register_sdmmc_mux_div()
239 	sdmmc_mux->div_flags = div_flags;  in tegra_clk_register_sdmmc_mux_div()
240 	sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;  in tegra_clk_register_sdmmc_mux_div()
242 	clk = clk_register(NULL, &sdmmc_mux->hw);  in tegra_clk_register_sdmmc_mux_div()
244 		kfree(sdmmc_mux);  in tegra_clk_register_sdmmc_mux_div()
248 	sdmmc_mux->gate.hw.clk = clk;  in tegra_clk_register_sdmmc_mux_div()