Lines Matching refs:dt_id
648 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
649 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
650 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
651 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
652 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
653 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
654 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
655 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
656 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
657 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
658 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
659 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
660 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
661 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
662 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
663 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
664 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
665 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
666 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
667 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
668 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
669 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
670 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
671 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
672 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
673 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
674 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
675 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
676 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
677 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
678 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
679 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
680 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
681 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
682 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
683 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
684 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
685 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
686 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
687 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
688 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
689 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
690 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
691 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
692 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
693 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
694 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
695 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
696 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
697 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
698 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
699 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
700 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
701 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
702 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
703 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
704 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
705 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
706 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
707 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
708 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
709 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
710 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
711 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
712 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
713 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
714 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
715 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
716 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
717 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
718 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
719 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
720 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
721 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
722 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
723 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
724 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
725 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
726 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
727 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
728 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
729 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
730 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
731 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
732 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
733 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
734 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
735 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
736 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
737 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
738 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
739 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
740 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
741 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
742 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
743 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
744 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
745 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
746 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
747 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
748 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
749 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
750 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
751 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
752 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
753 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
754 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
755 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
756 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
757 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
758 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
759 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
760 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
761 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
762 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
763 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
764 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
765 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
766 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
767 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
768 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
769 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
770 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
771 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
772 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
773 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
774 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
775 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
776 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
777 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
778 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
779 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
780 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
781 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
782 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
783 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
784 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
785 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
786 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
787 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
788 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
789 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
790 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
791 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
792 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
793 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
794 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
795 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
796 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
797 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
798 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
799 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
800 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
801 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
802 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
803 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
804 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
805 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
806 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
807 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
808 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
809 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
810 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
811 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
812 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
813 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
814 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
815 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
816 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
817 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
818 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
819 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
820 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
821 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
822 [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
826 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
827 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
828 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
829 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
830 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
831 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
832 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
833 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
834 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
835 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
836 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
837 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
838 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
839 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
840 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
841 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
842 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
843 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
844 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
845 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
846 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
847 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
848 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
849 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
850 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
851 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
852 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
853 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
854 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
855 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
856 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
857 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
858 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
859 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
860 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
861 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
862 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
863 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
864 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
865 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
866 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
867 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
868 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
869 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
870 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
871 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
872 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
873 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
874 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
875 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
876 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
877 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
878 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
879 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
880 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
881 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
882 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
883 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
884 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
885 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
886 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
887 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
888 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },