Lines Matching refs:TEGRA124_CLK_CLK_MAX
1260 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
1261 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
1264 { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
1277 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
1278 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
1282 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
1290 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
1291 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
1294 { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1295 { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1296 { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1297 { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1298 { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1299 { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1300 { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1302 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1307 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
1311 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1318 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1335 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra124_clock_apply_init_table()
1336 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra124_clock_apply_init_table()
1411 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra132_clock_apply_init_table()
1412 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX); in tegra132_clock_apply_init_table()
1450 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, in tegra124_132_clock_init_pre()