Lines Matching refs:pll_ref_div
587 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; in tegra20_clk_measure_input_freq() local
592 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
596 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
600 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
604 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
619 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div() local
622 switch (pll_ref_div) { in tegra20_get_pll_ref_div()
630 pr_err("Invalid pll ref divider %d\n", pll_ref_div); in tegra20_get_pll_ref_div()
896 unsigned int pll_ref_div; in tegra20_osc_clk_init() local
906 pll_ref_div = tegra20_get_pll_ref_div(); in tegra20_osc_clk_init()
908 CLK_SET_RATE_PARENT, 1, pll_ref_div); in tegra20_osc_clk_init()