Lines Matching refs:UTMIPLL_HW_PWRDN_CFG0

205 #define UTMIPLL_HW_PWRDN_CFG0			0x52c  macro
2715 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_put_utmipll_in_iddq()
2723 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_put_utmipll_in_iddq()
2731 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_put_utmipll_out_iddq()
2733 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_put_utmipll_out_iddq()
2753 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2755 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2809 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2812 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2823 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2825 	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_utmi_param_configure()
2916 	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);  in tegra210_init_pllu()