Lines Matching refs:params
672 struct tegra_clk_pll_params *params, in _pll_misc_chk_default() argument
675 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); in _pll_misc_chk_default()
683 params->defaults_set = false; in _pll_misc_chk_default()
692 static void pllcx_check_defaults(struct tegra_clk_pll_params *params) in pllcx_check_defaults() argument
697 _pll_misc_chk_default(clk_base, params, 0, default_val, in pllcx_check_defaults()
701 _pll_misc_chk_default(clk_base, params, 1, default_val, in pllcx_check_defaults()
705 _pll_misc_chk_default(clk_base, params, 2, default_val, in pllcx_check_defaults()
709 _pll_misc_chk_default(clk_base, params, 3, default_val, in pllcx_check_defaults()
716 pllcx->params->defaults_set = true; in tegra210_pllcx_set_defaults()
718 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
720 pllcx_check_defaults(pllcx->params); in tegra210_pllcx_set_defaults()
721 if (!pllcx->params->defaults_set) in tegra210_pllcx_set_defaults()
729 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
731 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
733 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
735 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
767 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
769 plla->params->defaults_set = true; in tegra210_plla_set_defaults()
778 plla->params->defaults_set = false; in tegra210_plla_set_defaults()
785 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
789 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
793 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
796 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
804 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
806 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
808 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
821 plld->params->defaults_set = true; in tegra210_plld_set_defaults()
823 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
831 _pll_misc_chk_default(clk_base, plld->params, 1, in tegra210_plld_set_defaults()
838 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
841 if (!plld->params->defaults_set) in tegra210_plld_set_defaults()
846 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
849 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
855 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
859 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
861 plld->params->ext_misc_reg[1]); in tegra210_plld_set_defaults()
873 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); in plldss_defaults()
875 plldss->params->defaults_set = true; in plldss_defaults()
885 plldss->params->defaults_set = false; in plldss_defaults()
890 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, in plldss_defaults()
899 if (plldss->params->ssc_ctrl_en_mask) { in plldss_defaults()
901 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
904 _pll_misc_chk_default(clk_base, plldss->params, 2, in plldss_defaults()
907 _pll_misc_chk_default(clk_base, plldss->params, 3, in plldss_defaults()
909 } else if (plldss->params->ext_misc_reg[1]) { in plldss_defaults()
911 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
916 if (!plldss->params->defaults_set) in plldss_defaults()
924 plldss->params->base_reg); in plldss_defaults()
927 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
930 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
939 writel_relaxed(val, clk_base + plldss->params->base_reg); in plldss_defaults()
942 if (!plldss->params->ext_misc_reg[1]) { in plldss_defaults()
944 plldss->params->ext_misc_reg[0]); in plldss_defaults()
950 plldss->params->ext_misc_reg[0]); in plldss_defaults()
953 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
954 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
955 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
992 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
994 pllre->params->defaults_set = true; in tegra210_pllre_set_defaults()
1009 pllre->params->defaults_set = false; in tegra210_pllre_set_defaults()
1015 _pll_misc_chk_default(clk_base, pllre->params, 0, val, in tegra210_pllre_set_defaults()
1019 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1022 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1031 writel_relaxed(val, clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1033 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1077 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, in pllx_check_defaults()
1081 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, in pllx_check_defaults()
1086 _pll_misc_chk_default(clk_base, pll->params, 2, in pllx_check_defaults()
1090 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, in pllx_check_defaults()
1094 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, in pllx_check_defaults()
1098 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, in pllx_check_defaults()
1107 pllx->params->defaults_set = true; in tegra210_pllx_set_defaults()
1116 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1124 if (!pllx->params->defaults_set) in tegra210_pllx_set_defaults()
1127 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1130 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1133 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1141 pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1145 pllx->params->ext_misc_reg[1]); in tegra210_pllx_set_defaults()
1148 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1152 pllx->params->ext_misc_reg[3]); in tegra210_pllx_set_defaults()
1156 pllx->params->ext_misc_reg[4]); in tegra210_pllx_set_defaults()
1158 pllx->params->ext_misc_reg[5]); in tegra210_pllx_set_defaults()
1165 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); in tegra210_pllmb_set_defaults()
1167 pllmb->params->defaults_set = true; in tegra210_pllmb_set_defaults()
1177 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, in tegra210_pllmb_set_defaults()
1180 if (!pllmb->params->defaults_set) in tegra210_pllmb_set_defaults()
1183 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1186 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1194 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1213 _pll_misc_chk_default(clk_base, pll->params, 0, val, in pllp_check_defaults()
1219 _pll_misc_chk_default(clk_base, pll->params, 1, val, in pllp_check_defaults()
1226 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1228 pllp->params->defaults_set = true; in tegra210_pllp_set_defaults()
1237 if (!pllp->params->defaults_set) in tegra210_pllp_set_defaults()
1241 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1245 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1253 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1256 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1260 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1270 static void pllu_check_defaults(struct tegra_clk_pll_params *params, in pllu_check_defaults() argument
1278 _pll_misc_chk_default(clk_base, params, 0, val, in pllu_check_defaults()
1283 _pll_misc_chk_default(clk_base, params, 1, val, in pllu_check_defaults()
1327 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1328 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1329 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1330 mask(p->params->div_nmp->divp_width))
1332 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1333 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1334 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1347 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { in tegra210_wait_for_mask()
1363 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) in tegra210_pllx_dyn_ramp()
1366 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1369 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1372 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1374 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1377 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], in tegra210_pllx_dyn_ramp()
1380 base = readl_relaxed(clk_base + pllx->params->base_reg) & in tegra210_pllx_dyn_ramp()
1382 base |= cfg->n << pllx->params->div_nmp->divn_shift; in tegra210_pllx_dyn_ramp()
1383 writel_relaxed(base, clk_base + pllx->params->base_reg); in tegra210_pllx_dyn_ramp()
1387 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1393 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); in tegra210_pllx_dyn_ramp()
1411 struct tegra_clk_pll_params *params = pll->params; in tegra210_pll_fixed_mdiv_cfg() local
1419 if (!(params->flags & TEGRA_PLL_VCO_OUT)) { in tegra210_pll_fixed_mdiv_cfg()
1420 p = DIV_ROUND_UP(params->vco_min, rate); in tegra210_pll_fixed_mdiv_cfg()
1421 p = params->round_p_to_pdiv(p, &pdiv); in tegra210_pll_fixed_mdiv_cfg()
1423 p = rate >= params->vco_min ? 1 : -EINVAL; in tegra210_pll_fixed_mdiv_cfg()
1436 if (p_rate > params->vco_max) in tegra210_pll_fixed_mdiv_cfg()
1437 p_rate = params->vco_max; in tegra210_pll_fixed_mdiv_cfg()
1443 if (params->sdm_ctrl_reg) { in tegra210_pll_fixed_mdiv_cfg()
1446 if (rem || params->ssc_ctrl_reg) { in tegra210_pll_fixed_mdiv_cfg()
1483 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, in tegra210_clk_adjust_vco_min() argument
1486 unsigned long vco_min = params->vco_min; in tegra210_clk_adjust_vco_min()
1488 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); in tegra210_clk_adjust_vco_min()
1489 vco_min = min(vco_min, params->vco_min); in tegra210_clk_adjust_vco_min()
2845 pllu.params = &pll_u_vco_params; in tegra210_enable_pllu()
2846 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2847 reg &= ~BIT(pllu.params->iddq_bit_idx); in tegra210_enable_pllu()
2848 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()