Lines Matching refs:TEGRA30_CLK_PLL_P
548 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
814 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
1233 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1234 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1235 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1236 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1237 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1249 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1250 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1251 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1254 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1255 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1256 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1257 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1258 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1259 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1262 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1263 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1277 { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
1278 { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },