clk/ti/clk-7xx.c

57 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
58 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
59 	{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
80 	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
85 	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
90 	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
95 	{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
106 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
169 	{ 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
170 	{ 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
268 	{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
285 	{ 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
350 	{ 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
351 	{ 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
392 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
397 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
402 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
407 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
412 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
417 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
447 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
452 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
457 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
483 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
500 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
506 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
527 	{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
533 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
538 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
543 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
548 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
553 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
555 	{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
560 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
561 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
566 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
571 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
572 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
577 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
578 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
583 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
584 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
589 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
594 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
599 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
604 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
605 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
610 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
611 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
682 	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
687 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
698 	{ 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },