52 	const struct dpll_data *dd;  in _omap3_dpll_write_clken()  local
55 	dd = clk->dpll_data;  in _omap3_dpll_write_clken()
57 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in _omap3_dpll_write_clken()
58 	v &= ~dd->enable_mask;  in _omap3_dpll_write_clken()
59 	v |= clken_bits << __ffs(dd->enable_mask);  in _omap3_dpll_write_clken()
60 	ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in _omap3_dpll_write_clken()
66 	const struct dpll_data *dd;  in _omap3_wait_dpll_status()  local
71 	dd = clk->dpll_data;  in _omap3_wait_dpll_status()
74 	state <<= __ffs(dd->idlest_mask);  in _omap3_wait_dpll_status()
76 	while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)  in _omap3_wait_dpll_status()
143 	const struct dpll_data *dd;  in _omap3_noncore_dpll_lock()  local
150 	dd = clk->dpll_data;  in _omap3_noncore_dpll_lock()
151 	state <<= __ffs(dd->idlest_mask);  in _omap3_noncore_dpll_lock()
154 	if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==  in _omap3_noncore_dpll_lock()
307 	struct dpll_data *dd = clk->dpll_data;  in omap3_noncore_dpll_program()  local
320 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
321 		v &= ~dd->freqsel_mask;  in omap3_noncore_dpll_program()
322 		v |= freqsel << __ffs(dd->freqsel_mask);  in omap3_noncore_dpll_program()
323 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
327 	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);  in omap3_noncore_dpll_program()
330 	if (dd->dcc_mask) {  in omap3_noncore_dpll_program()
331 		if (dd->last_rounded_rate >= dd->dcc_rate)  in omap3_noncore_dpll_program()
332 			v |= dd->dcc_mask; /* Enable DCC */  in omap3_noncore_dpll_program()
334 			v &= ~dd->dcc_mask; /* Disable DCC */  in omap3_noncore_dpll_program()
337 	v &= ~(dd->mult_mask | dd->div1_mask);  in omap3_noncore_dpll_program()
338 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);  in omap3_noncore_dpll_program()
339 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);  in omap3_noncore_dpll_program()
342 	if (dd->dco_mask) {  in omap3_noncore_dpll_program()
343 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);  in omap3_noncore_dpll_program()
344 		v &= ~(dd->dco_mask);  in omap3_noncore_dpll_program()
345 		v |= dco << __ffs(dd->dco_mask);  in omap3_noncore_dpll_program()
347 	if (dd->sddiv_mask) {  in omap3_noncore_dpll_program()
348 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,  in omap3_noncore_dpll_program()
349 			      dd->last_rounded_n);  in omap3_noncore_dpll_program()
350 		v &= ~(dd->sddiv_mask);  in omap3_noncore_dpll_program()
351 		v |= sd_div << __ffs(dd->sddiv_mask);  in omap3_noncore_dpll_program()
373 	ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);  in omap3_noncore_dpll_program()
376 	if (dd->m4xen_mask || dd->lpmode_mask) {  in omap3_noncore_dpll_program()
377 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);  in omap3_noncore_dpll_program()
379 		if (dd->m4xen_mask) {  in omap3_noncore_dpll_program()
380 			if (dd->last_rounded_m4xen)  in omap3_noncore_dpll_program()
381 				v |= dd->m4xen_mask;  in omap3_noncore_dpll_program()
383 				v &= ~dd->m4xen_mask;  in omap3_noncore_dpll_program()
386 		if (dd->lpmode_mask) {  in omap3_noncore_dpll_program()
387 			if (dd->last_rounded_lpmode)  in omap3_noncore_dpll_program()
388 				v |= dd->lpmode_mask;  in omap3_noncore_dpll_program()
390 				v &= ~dd->lpmode_mask;  in omap3_noncore_dpll_program()
393 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);  in omap3_noncore_dpll_program()
443 	struct dpll_data *dd;  in omap3_noncore_dpll_enable()  local
446 	dd = clk->dpll_data;  in omap3_noncore_dpll_enable()
447 	if (!dd)  in omap3_noncore_dpll_enable()
463 	if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {  in omap3_noncore_dpll_enable()
464 		WARN_ON(parent != dd->clk_bypass);  in omap3_noncore_dpll_enable()
467 		WARN_ON(parent != dd->clk_ref);  in omap3_noncore_dpll_enable()
506 	struct dpll_data *dd;  in omap3_noncore_dpll_determine_rate()  local
511 	dd = clk->dpll_data;  in omap3_noncore_dpll_determine_rate()
512 	if (!dd)  in omap3_noncore_dpll_determine_rate()
515 	if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&  in omap3_noncore_dpll_determine_rate()
516 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {  in omap3_noncore_dpll_determine_rate()
517 		req->best_parent_hw = dd->clk_bypass;  in omap3_noncore_dpll_determine_rate()
521 		req->best_parent_hw = dd->clk_ref;  in omap3_noncore_dpll_determine_rate()
568 	struct dpll_data *dd;  in omap3_noncore_dpll_set_rate()  local
575 	dd = clk->dpll_data;  in omap3_noncore_dpll_set_rate()
576 	if (!dd)  in omap3_noncore_dpll_set_rate()
579 	if (clk_hw_get_parent(hw) != dd->clk_ref)  in omap3_noncore_dpll_set_rate()
582 	if (dd->last_rounded_rate == 0)  in omap3_noncore_dpll_set_rate()
587 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);  in omap3_noncore_dpll_set_rate()
647 	const struct dpll_data *dd;  in omap3_dpll_autoidle_read()  local
653 	dd = clk->dpll_data;  in omap3_dpll_autoidle_read()
655 	if (!dd->autoidle_mask)  in omap3_dpll_autoidle_read()
658 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_autoidle_read()
659 	v &= dd->autoidle_mask;  in omap3_dpll_autoidle_read()
660 	v >>= __ffs(dd->autoidle_mask);  in omap3_dpll_autoidle_read()
676 	const struct dpll_data *dd;  in omap3_dpll_allow_idle()  local
682 	dd = clk->dpll_data;  in omap3_dpll_allow_idle()
684 	if (!dd->autoidle_mask)  in omap3_dpll_allow_idle()
692 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_allow_idle()
693 	v &= ~dd->autoidle_mask;  in omap3_dpll_allow_idle()
694 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);  in omap3_dpll_allow_idle()
695 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_allow_idle()
706 	const struct dpll_data *dd;  in omap3_dpll_deny_idle()  local
712 	dd = clk->dpll_data;  in omap3_dpll_deny_idle()
714 	if (!dd->autoidle_mask)  in omap3_dpll_deny_idle()
717 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);  in omap3_dpll_deny_idle()
718 	v &= ~dd->autoidle_mask;  in omap3_dpll_deny_idle()
719 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);  in omap3_dpll_deny_idle()
720 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);  in omap3_dpll_deny_idle()
759 	const struct dpll_data *dd;  in omap3_clkoutx2_recalc()  local
772 	dd = pclk->dpll_data;  in omap3_clkoutx2_recalc()
774 	WARN_ON(!dd->enable_mask);  in omap3_clkoutx2_recalc()
776 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;  in omap3_clkoutx2_recalc()
777 	v >>= __ffs(dd->enable_mask);  in omap3_clkoutx2_recalc()
778 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))  in omap3_clkoutx2_recalc()
866 	struct dpll_data *dd;  in omap3_dpll5_apply_errata()  local
880 	dd = clk->dpll_data;  in omap3_dpll5_apply_errata()
881 	dd->last_rounded_m = d->m;  in omap3_dpll5_apply_errata()
882 	dd->last_rounded_n = d->n;  in omap3_dpll5_apply_errata()
883 	dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);  in omap3_dpll5_apply_errata()