Lines Matching refs:MPC_I2C_SR
43 #define MPC_I2C_SR 0x0c macro
95 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) { in mpc_i2c_isr()
97 i2c->interrupt = readb(i2c->base + MPC_I2C_SR); in mpc_i2c_isr()
98 writeb(0, i2c->base + MPC_I2C_SR); in mpc_i2c_isr()
117 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */ in mpc_i2c_fixup()
141 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { in i2c_wait()
150 cmd_err = readb(i2c->base + MPC_I2C_SR); in i2c_wait()
151 writeb(0, i2c->base + MPC_I2C_SR); in i2c_wait()
191 void __iomem *addr = i2c->base + MPC_I2C_SR; in i2c_mpc_wait_sr()
229 val = readb(i2c->base + MPC_I2C_SR); in mpc_i2c_fixup_A004447()
535 writeb(0, i2c->base + MPC_I2C_SR); in mpc_i2c_start()
655 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { in mpc_xfer()
662 u8 status = readb(i2c->base + MPC_I2C_SR); in mpc_xfer()
667 i2c->base + MPC_I2C_SR); in mpc_xfer()
696 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) { in mpc_xfer()
698 u8 status = readb(i2c->base + MPC_I2C_SR); in mpc_xfer()
703 i2c->base + MPC_I2C_SR); in mpc_xfer()