27 #define REG_CR		0x00  macro
153 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
155 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
157 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
159 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
174 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
176 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
200 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
206 				writew(CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_write()
210 			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_write()
232 	val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
234 	writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
236 	val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
238 	writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
241 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
243 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
247 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
249 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
264 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
266 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
284 			val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
286 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
288 			val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
290 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
358 	writew(0, i2c_dev->base + REG_CR);  in wmt_i2c_reset_hardware()
362 	writew(CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_reset_hardware()