80 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));  in ReadISAC()
86 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);  in WriteISAC()
92 	readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);  in ReadISACfifo()
98 	writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);  in WriteISACfifo()
105 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));  in ReadHSCX()
111 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);  in WriteHSCX()
119 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,  in set_ipac_active()
128 				      cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
130 					      cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
132 						cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
134 						  cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
146 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);  in bkm_interrupt_ipac()
155 		val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);  in bkm_interrupt_ipac()
167 		val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);  in bkm_interrupt_ipac()
176 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);  in bkm_interrupt_ipac()
184 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);  in bkm_interrupt_ipac()
185 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);  in bkm_interrupt_ipac()
406 	cs->hw.ax.data_adr = cs->hw.ax.base + 4;  in setup_sct_quadro()
413 	       cs->hw.ax.data_adr,  in setup_sct_quadro()
431 	       readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));  in setup_sct_quadro()