74 	return (ReadReg(cs, HFCD_DATA, offset));  in readreghfcd()
80 	WriteReg(cs, HFCD_DATA, offset, value);  in writereghfcd()
88 	while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) {  in WaitForBusy()
137 	cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0);  in SelFiFo()
176 	val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH);  in ReadZReg()
178 	val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW);  in ReadZReg()
234 			chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);  in hfc_empty_fifo()
236 			chksum += ReadReg(cs, HFCD_DATA, cip);  in hfc_empty_fifo()
238 			stat = ReadReg(cs, HFCD_DATA, cip);  in hfc_empty_fifo()
254 	stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC |  in hfc_empty_fifo()
275 	bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip);  in hfc_fill_fifo()
279 	bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip);  in hfc_fill_fifo()
332 	ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel));  in hfc_fill_fifo()
368 	f1 = ReadReg(cs, HFCD_DATA, cip);  in main_rec_2bds0()
371 	f2 = ReadReg(cs, HFCD_DATA, cip);  in main_rec_2bds0()
447 	WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl);  in mode_2bs0()
448 	WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt);  in mode_2bs0()
449 	WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn);  in mode_2bs0()
653 				chksum = (ReadReg(cs, HFCD_DATA, cip) << 8);  in receive_dmsg()
655 				chksum += ReadReg(cs, HFCD_DATA, cip);  in receive_dmsg()
657 				stat = ReadReg(cs, HFCD_DATA, cip);  in receive_dmsg()
678 		stat = ReadReg(cs, HFCD_DATA, cip);  in receive_dmsg()
703 	cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf;  in hfc_fill_dfifo()
706 	cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf;  in hfc_fill_dfifo()
746 	ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND);  in hfc_fill_dfifo()