Lines Matching refs:hfcpci
76 cs->hw.hfcpci.pci_io); in release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
84 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmast… in release_io_hfcpci()
85 del_timer(&cs->hw.hfcpci.timer); in release_io_hfcpci()
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in release_io_hfcpci()
87 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in release_io_hfcpci()
88 cs->hw.hfcpci.fifos = NULL; in release_io_hfcpci()
89 iounmap((void *)cs->hw.hfcpci.pci_io); in release_io_hfcpci()
99 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in reset_hfcpci()
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in reset_hfcpci()
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
104 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable m… in reset_hfcpci()
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */ in reset_hfcpci()
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in reset_hfcpci()
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcpci()
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in reset_hfcpci()
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE; in reset_hfcpci()
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ in reset_hfcpci()
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */ in reset_hfcpci()
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */ in reset_hfcpci()
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; in reset_hfcpci()
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in reset_hfcpci()
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | in reset_hfcpci()
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in reset_hfcpci()
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */ in reset_hfcpci()
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in reset_hfcpci()
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcpci()
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in reset_hfcpci()
141 cs->hw.hfcpci.sctrl_r = 0; in reset_hfcpci()
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in reset_hfcpci()
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */ in reset_hfcpci()
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in reset_hfcpci()
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE; in reset_hfcpci()
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
170 struct IsdnCardState *cs = from_timer(cs, t, hw.hfcpci.timer); in hfcpci_Timer()
171 cs->hw.hfcpci.timer.expires = jiffies + 75; in hfcpci_Timer()
222 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in hfcpci_clear_fifo_rx()
223 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX; in hfcpci_clear_fifo_rx()
225 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in hfcpci_clear_fifo_rx()
226 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX; in hfcpci_clear_fifo_rx()
229 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_rx()
230 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
231 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0; in hfcpci_clear_fifo_rx()
237 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_rx()
238 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
249 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_clear_fifo_tx()
250 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX; in hfcpci_clear_fifo_tx()
252 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_clear_fifo_tx()
253 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX; in hfcpci_clear_fifo_tx()
256 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_tx()
257 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
263 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_tx()
264 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
340 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx; in receive_dmsg()
462 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in main_rec_hfcpci()
463 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in main_rec_hfcpci()
464 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in main_rec_hfcpci()
467 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in main_rec_hfcpci()
468 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1; in main_rec_hfcpci()
497 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) { in main_rec_hfcpci()
501 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt; in main_rec_hfcpci()
531 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx; in hfcpci_fill_dfifo()
604 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in hfcpci_fill_fifo()
605 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_fill_fifo()
606 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2; in hfcpci_fill_fifo()
608 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_fill_fifo()
609 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1; in hfcpci_fill_fifo()
776 …(!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_… in hfcpci_auxcmd()
781 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT; in hfcpci_auxcmd()
782 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ in hfcpci_auxcmd()
787 cs->dc.hfcpci.ph_state = 1; in hfcpci_auxcmd()
788 cs->hw.hfcpci.nt_mode = 1; in hfcpci_auxcmd()
789 cs->hw.hfcpci.nt_timer = 0; in hfcpci_auxcmd()
795 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) || in hfcpci_auxcmd()
796 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12)) in hfcpci_auxcmd()
802 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */ in hfcpci_auxcmd()
803 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
804 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
807 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */ in hfcpci_auxcmd()
808 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
809 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
811 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
812 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
813 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcpci_auxcmd()
814 cs->hw.hfcpci.ctmt &= ~2; in hfcpci_auxcmd()
815 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in hfcpci_auxcmd()
816 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in hfcpci_auxcmd()
818 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in hfcpci_auxcmd()
819 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_auxcmd()
821 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_auxcmd()
841 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in receive_emsg()
842 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in receive_emsg()
938 if (!(cs->hw.hfcpci.int_m2 & 0x08)) { in hfcpci_interrupt()
939 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2); in hfcpci_interrupt()
955 val &= cs->hw.hfcpci.int_m1; in hfcpci_interrupt()
959 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state, in hfcpci_interrupt()
961 cs->dc.hfcpci.ph_state = exval; in hfcpci_interrupt()
966 if (cs->hw.hfcpci.nt_mode) { in hfcpci_interrupt()
967 if ((--cs->hw.hfcpci.nt_timer) < 0) in hfcpci_interrupt()
971 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_interrupt()
975 cs->hw.hfcpci.int_s1 |= val; in hfcpci_interrupt()
979 if (cs->hw.hfcpci.int_s1 & 0x18) { in hfcpci_interrupt()
981 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
982 cs->hw.hfcpci.int_s1 = exval; in hfcpci_interrupt()
985 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
1001 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
1083 if (cs->hw.hfcpci.int_s1 && count--) { in hfcpci_interrupt()
1084 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
1085 cs->hw.hfcpci.int_s1 = 0; in hfcpci_interrupt()
1186 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1187 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1199 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER; in HFCPCI_l1hw()
1200 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1205 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1206 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1215 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1; in HFCPCI_l1hw()
1216 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1222 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08; in HFCPCI_l1hw()
1223 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1232 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */ in HFCPCI_l1hw()
1233 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in HFCPCI_l1hw()
1283 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1284 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1288 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcpci()
1289 cs->hw.hfcpci.sctrl_e |= 0x80; in mode_hfcpci()
1291 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1292 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1296 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1297 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1303 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in mode_hfcpci()
1304 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcpci()
1306 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA; in mode_hfcpci()
1307 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcpci()
1310 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1311 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1313 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1314 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1321 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1322 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1324 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1325 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1328 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1329 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1330 cs->hw.hfcpci.ctmt |= 2; in mode_hfcpci()
1331 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1333 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1334 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1335 cs->hw.hfcpci.ctmt |= 1; in mode_hfcpci()
1336 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1343 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1344 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1346 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1347 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1350 cs->hw.hfcpci.last_bfifo_cnt[1] = 0; in mode_hfcpci()
1351 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1352 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1353 cs->hw.hfcpci.ctmt &= ~2; in mode_hfcpci()
1354 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1356 cs->hw.hfcpci.last_bfifo_cnt[0] = 0; in mode_hfcpci()
1357 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1358 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1359 cs->hw.hfcpci.ctmt &= ~1; in mode_hfcpci()
1360 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1365 cs->hw.hfcpci.conn |= 0x10; in mode_hfcpci()
1366 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1367 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1368 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1369 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1371 cs->hw.hfcpci.conn |= 0x02; in mode_hfcpci()
1372 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1373 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1374 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1375 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1379 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); in mode_hfcpci()
1380 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in mode_hfcpci()
1381 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in mode_hfcpci()
1382 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in mode_hfcpci()
1383 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in mode_hfcpci()
1384 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in mode_hfcpci()
1385 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in mode_hfcpci()
1514 if (!cs->hw.hfcpci.nt_mode) in hfcpci_bh()
1515 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1535 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1537 if (cs->hw.hfcpci.nt_timer < 0) { in hfcpci_bh()
1538 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1539 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1540 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1546 cs->dc.hfcpci.ph_state = 4; in hfcpci_bh()
1548 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER; in hfcpci_bh()
1549 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1550 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER; in hfcpci_bh()
1551 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125; in hfcpci_bh()
1552 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1553 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1554 cs->hw.hfcpci.nt_timer = NT_T1_COUNT; in hfcpci_bh()
1561 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1562 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1563 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1622 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_card_msg()
1623 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_card_msg()
1625 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in hfcpci_card_msg()
1650 cs->hw.hfcpci.int_s1 = 0; in setup_hfcpci()
1651 cs->dc.hfcpci.ph_state = 0; in setup_hfcpci()
1652 cs->hw.hfcpci.fifo = 255; in setup_hfcpci()
1691 cs->hw.hfcpci.dev = dev_hfcpci; in setup_hfcpci()
1697 cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start; in setup_hfcpci()
1700 if (!cs->hw.hfcpci.pci_io) { in setup_hfcpci()
1706 cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev, in setup_hfcpci()
1707 0x8000, &cs->hw.hfcpci.dma); in setup_hfcpci()
1708 if (!cs->hw.hfcpci.fifos) { in setup_hfcpci()
1712 if (cs->hw.hfcpci.dma & 0x7fff) { in setup_hfcpci()
1715 (u_long)cs->hw.hfcpci.dma); in setup_hfcpci()
1716 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in setup_hfcpci()
1717 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in setup_hfcpci()
1720 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma); in setup_hfcpci()
1721 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256); in setup_hfcpci()
1724 cs->hw.hfcpci.pci_io, in setup_hfcpci()
1725 cs->hw.hfcpci.fifos, in setup_hfcpci()
1726 (u_long)cs->hw.hfcpci.dma, in setup_hfcpci()
1731 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in setup_hfcpci()
1732 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */ in setup_hfcpci()
1733 cs->hw.hfcpci.int_m1 = 0; in setup_hfcpci()
1734 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in setup_hfcpci()
1735 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in setup_hfcpci()
1750 timer_setup(&cs->hw.hfcpci.timer, hfcpci_Timer, 0); in setup_hfcpci()