Lines Matching refs:HFCD_DATA
30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { in hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); in hfcs_interrupt()
70 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ in reset_hfcs()
75 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ in reset_hfcs()
81 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); in reset_hfcs()
82 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e); in reset_hfcs()
83 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */ in reset_hfcs()
85 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); in reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); in reset_hfcs()
91 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); in reset_hfcs()
92 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcs()
94 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */ in reset_hfcs()
96 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */ in reset_hfcs()
98 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); in reset_hfcs()
129 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); in hfcs_card_msg()
130 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); in hfcs_card_msg()