67 	cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);  in ph_command()
163 		cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1  in dch_l2l1()
164 		cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1  in dch_l2l1()
168 			cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a);  in dch_l2l1()
171 			cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a);  in dch_l2l1()
174 			cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14);  in dch_l2l1()
177 			cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14);  in dch_l2l1()
228 			cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR  in dbusy_timer_handler()
248 		cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC  in dch_empty_fifo()
257 	cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC  in dch_empty_fifo()
295 	cs->writeisac(cs, IPACX_CMDRD, cmd);  in dch_fill_fifo()
341 			cs->writeisac(cs, IPACX_CMDRD, 0x80);  // RMC  in dch_int()
368 		cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES  in dch_int()
429 	cs->writeisac(cs, IPACX_TR_CONF0, 0x00);  // clear LDD  in dch_init()
430 	cs->writeisac(cs, IPACX_TR_CONF2, 0x00);  // enable transmitter  in dch_init()
431 	cs->writeisac(cs, IPACX_MODED,    0xC9);  // transparent mode 0, RAC, stop/go  in dch_init()
432 	cs->writeisac(cs, IPACX_MON_CR,   0x00);  // disable monitor channel  in dch_init()
727 		cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);  in bch_mode()
728 		cs->writeisac(cs, IPACX_BCHA_CR,       0x88);  in bch_mode()
732 		cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);  in bch_mode()
733 		cs->writeisac(cs, IPACX_BCHB_CR,       0x88);  in bch_mode()
871 	cs->writeisac(cs, IPACX_MASK, 0xff);  in clear_pending_ints()
872 	cs->writeisac(cs, IPACX_MASKD, 0xff);  in clear_pending_ints()
902 		cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);  in init_ipacx()
903 		cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register  in init_ipacx()
906 		cs->writeisac(cs, IPACX_CMDRD, 0x41);  in init_ipacx()