Lines Matching refs:hscx_ale
102 return (readreg(cs->hw.ix1.hscx_ale, in ReadHSCX()
109 writereg(cs->hw.ix1.hscx_ale, in WriteHSCX()
113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
118 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale, \
121 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale, \
134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); in ix1micro_interrupt()
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); in ix1micro_interrupt()
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); in ix1micro_interrupt()
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); in ix1micro_interrupt()
159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); in ix1micro_interrupt()
281 cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET; in setup_ix1micro()