78 	return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset));  in ReadISAC()
84 	writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value);  in WriteISAC()
90 	readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size);  in ReadISACfifo()
96 	writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size);  in WriteISACfifo()
102 	return (readreg(cs->hw.ix1.hscx_ale,  in ReadHSCX()
103 			cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0)));  in ReadHSCX()
109 	writereg(cs->hw.ix1.hscx_ale,  in WriteHSCX()
110 		 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value);  in WriteHSCX()
113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale,		\
114 				      cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale,	\
116 					      cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
118 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale,	\
119 						cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
121 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale,	\
122 						  cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
134 	val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);  in ix1micro_interrupt()
138 	val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA);  in ix1micro_interrupt()
142 	val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40);  in ix1micro_interrupt()
148 	val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA);  in ix1micro_interrupt()
154 	writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF);  in ix1micro_interrupt()
155 	writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF);  in ix1micro_interrupt()
156 	writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF);  in ix1micro_interrupt()
157 	writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0);  in ix1micro_interrupt()
158 	writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0);  in ix1micro_interrupt()
159 	writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0);  in ix1micro_interrupt()
167 	if (cs->hw.ix1.cfg_reg)  in release_io_ix1micro()
168 		release_region(cs->hw.ix1.cfg_reg, 4);  in release_io_ix1micro()
179 		byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1);  in ix1_reset()
182 	byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0);  in ix1_reset()
280 	cs->hw.ix1.isac_ale = card->para[1] + ISAC_COMMAND_OFFSET;  in setup_ix1micro()
281 	cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET;  in setup_ix1micro()
282 	cs->hw.ix1.isac = card->para[1] + ISAC_DATA_OFFSET;  in setup_ix1micro()
283 	cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET;  in setup_ix1micro()
284 	cs->hw.ix1.cfg_reg = card->para[1];  in setup_ix1micro()
286 	if (cs->hw.ix1.cfg_reg) {  in setup_ix1micro()
287 		if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) {  in setup_ix1micro()
291 			       cs->hw.ix1.cfg_reg,  in setup_ix1micro()
292 			       cs->hw.ix1.cfg_reg + 4);  in setup_ix1micro()
297 	       cs->irq, cs->hw.ix1.cfg_reg);  in setup_ix1micro()