Lines Matching refs:state
148 static int i2cread(struct mxl *state, u8 *data, int len) in i2cread() argument
150 return i2c_read(state->base->i2c, state->base->adr, data, len); in i2cread()
153 static int i2cwrite(struct mxl *state, u8 *data, int len) in i2cwrite() argument
155 return i2c_write(state->base->i2c, state->base->adr, data, len); in i2cwrite()
158 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) in read_register_unlocked() argument
167 stat = i2cwrite(state, data, in read_register_unlocked()
170 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register_unlocked()
172 stat = i2cread(state, (u8 *) val, in read_register_unlocked()
176 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register_unlocked()
183 static int send_command(struct mxl *state, u32 size, u8 *buf) in send_command() argument
188 mutex_lock(&state->base->i2c_lock); in send_command()
189 if (state->base->fwversion > 0x02010109) { in send_command()
190 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); in send_command()
192 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
194 mutex_unlock(&state->base->i2c_lock); in send_command()
196 mutex_lock(&state->base->i2c_lock); in send_command()
197 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, in send_command()
201 dev_info(state->i2cdev, "%s busy\n", __func__); in send_command()
202 mutex_unlock(&state->base->i2c_lock); in send_command()
206 stat = i2cwrite(state, buf, size); in send_command()
207 mutex_unlock(&state->base->i2c_lock); in send_command()
211 static int write_register(struct mxl *state, u32 reg, u32 val) in write_register() argument
219 mutex_lock(&state->base->i2c_lock); in write_register()
220 stat = i2cwrite(state, data, sizeof(data)); in write_register()
221 mutex_unlock(&state->base->i2c_lock); in write_register()
223 dev_err(state->i2cdev, "i2c write error\n"); in write_register()
227 static int write_firmware_block(struct mxl *state, in write_firmware_block() argument
231 u8 *buf = state->base->buf; in write_firmware_block()
233 mutex_lock(&state->base->i2c_lock); in write_firmware_block()
241 stat = i2cwrite(state, buf, in write_firmware_block()
244 mutex_unlock(&state->base->i2c_lock); in write_firmware_block()
246 dev_err(state->i2cdev, "fw block write failed\n"); in write_firmware_block()
250 static int read_register(struct mxl *state, u32 reg, u32 *val) in read_register() argument
259 mutex_lock(&state->base->i2c_lock); in read_register()
260 stat = i2cwrite(state, data, in read_register()
263 dev_err(state->i2cdev, "i2c read error 1\n"); in read_register()
265 stat = i2cread(state, (u8 *) val, in read_register()
267 mutex_unlock(&state->base->i2c_lock); in read_register()
270 dev_err(state->i2cdev, "i2c read error 2\n"); in read_register()
274 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) in read_register_block() argument
277 u8 *buf = state->base->buf; in read_register_block()
279 mutex_lock(&state->base->i2c_lock); in read_register_block()
287 stat = i2cwrite(state, buf, in read_register_block()
290 stat = i2cread(state, data, size); in read_register_block()
293 mutex_unlock(&state->base->i2c_lock); in read_register_block()
297 static int read_by_mnemonic(struct mxl *state, in read_by_mnemonic() argument
303 stat = read_register(state, reg, &data); in read_by_mnemonic()
314 static int update_by_mnemonic(struct mxl *state, in update_by_mnemonic() argument
320 stat = read_register(state, reg, &data); in update_by_mnemonic()
325 stat = write_register(state, reg, data); in update_by_mnemonic()
329 static int firmware_is_alive(struct mxl *state) in firmware_is_alive() argument
333 if (read_register(state, HYDRA_HEAR_BEAT, &hb0)) in firmware_is_alive()
336 if (read_register(state, HYDRA_HEAR_BEAT, &hb1)) in firmware_is_alive()
366 struct mxl *state = fe->demodulator_priv; in release() local
368 list_del(&state->mxl); in release()
370 state->base->count--; in release()
371 if (state->base->count == 0) { in release()
372 list_del(&state->base->mxllist); in release()
373 kfree(state->base); in release()
375 kfree(state); in release()
394 static int cfg_scrambler(struct mxl *state, u32 gold) in cfg_scrambler() argument
400 state->demod, 0, 0, 0, in cfg_scrambler()
412 return send_command(state, sizeof(buf), buf); in cfg_scrambler()
415 static int cfg_demod_abort_tune(struct mxl *state) in cfg_demod_abort_tune() argument
421 abort_tune_cmd.demod_id = state->demod; in cfg_demod_abort_tune()
424 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in cfg_demod_abort_tune()
438 struct mxl *state = fe->demodulator_priv; in set_parameters() local
472 cfg_scrambler(state, p->scrambling_sequence_index); in set_parameters()
477 demod_chan_cfg.tuner_index = state->tuner; in set_parameters()
478 demod_chan_cfg.demod_index = state->demod; in set_parameters()
485 mutex_lock(&state->base->tune_lock); in set_parameters()
487 state->base->next_tune)) in set_parameters()
488 while (time_before(jiffies, state->base->next_tune)) in set_parameters()
490 state->base->next_tune = jiffies + msecs_to_jiffies(100); in set_parameters()
491 state->tuner_in_use = state->tuner; in set_parameters()
494 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in set_parameters()
496 mutex_unlock(&state->base->tune_lock); in set_parameters()
500 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
504 struct mxl *state = fe->demodulator_priv; in sleep() local
507 cfg_demod_abort_tune(state); in sleep()
508 if (state->tuner_in_use != 0xffffffff) { in sleep()
509 mutex_lock(&state->base->tune_lock); in sleep()
510 state->tuner_in_use = 0xffffffff; in sleep()
511 list_for_each_entry(p, &state->base->mxls, mxl) { in sleep()
512 if (p->tuner_in_use == state->tuner) in sleep()
515 if (&p->mxl == &state->base->mxls) in sleep()
516 enable_tuner(state, state->tuner, 0); in sleep()
517 mutex_unlock(&state->base->tune_lock); in sleep()
524 struct mxl *state = fe->demodulator_priv; in read_snr() local
529 mutex_lock(&state->base->status_lock); in read_snr()
530 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_snr()
531 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET + in read_snr()
532 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_snr()
534 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_snr()
535 mutex_unlock(&state->base->status_lock); in read_snr()
545 struct mxl *state = fe->demodulator_priv; in read_ber() local
549 mutex_lock(&state->base->status_lock); in read_ber()
550 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_ber()
551 read_register_block(state, in read_ber()
553 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
556 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_ber()
570 read_register_block(state, in read_ber()
572 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_ber()
594 mutex_unlock(&state->base->status_lock); in read_ber()
601 struct mxl *state = fe->demodulator_priv; in read_signal_strength() local
606 mutex_lock(&state->base->status_lock); in read_signal_strength()
607 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_signal_strength()
608 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR + in read_signal_strength()
609 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_signal_strength()
611 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_signal_strength()
612 mutex_unlock(&state->base->status_lock); in read_signal_strength()
622 struct mxl *state = fe->demodulator_priv; in read_status() local
626 mutex_lock(&state->base->status_lock); in read_status()
627 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in read_status()
628 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET + in read_status()
629 HYDRA_DMD_STATUS_OFFSET(state->demod)), in read_status()
631 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in read_status()
632 mutex_unlock(&state->base->status_lock); in read_status()
662 struct mxl *state = fe->demodulator_priv; in tune() local
670 state->tune_time = jiffies; in tune()
692 struct mxl *state = fe->demodulator_priv; in get_frontend() local
696 mutex_lock(&state->base->status_lock); in get_frontend()
697 HYDRA_DEMOD_STATUS_LOCK(state, state->demod); in get_frontend()
698 read_register_block(state, in get_frontend()
700 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
704 read_register_block(state, in get_frontend()
706 HYDRA_DMD_STATUS_OFFSET(state->demod)), in get_frontend()
709 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); in get_frontend()
710 mutex_unlock(&state->base->status_lock); in get_frontend()
712 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n", in get_frontend()
777 struct mxl *state = fe->demodulator_priv; in set_input() local
779 state->tuner = input; in set_input()
816 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable) in cfg_dev_xtal() argument
818 if (state->base->can_clkout || !enable) in cfg_dev_xtal()
819 update_by_mnemonic(state, 0x90200054, 23, 1, enable); in cfg_dev_xtal()
822 write_register(state, HYDRA_CRYSTAL_SETTING, 0); in cfg_dev_xtal()
824 write_register(state, HYDRA_CRYSTAL_SETTING, 1); in cfg_dev_xtal()
826 write_register(state, HYDRA_CRYSTAL_CAP, cap); in cfg_dev_xtal()
850 static int write_fw_segment(struct mxl *state, in write_fw_segment() argument
874 status = write_firmware_block(state, mem_addr, size, w_buf_ptr); in write_fw_segment()
885 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr, in do_firmware_download() argument
898 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n", in do_firmware_download()
902 status = write_register(state, FW_DL_SIGN_ADDR, 0); in do_firmware_download()
908 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n", in do_firmware_download()
917 if (state->base->type == MXL_HYDRA_DEVICE_568) { in do_firmware_download()
921 update_by_mnemonic(state, 0x8003003C, 0, 1, 1); in do_firmware_download()
923 write_register(state, 0x90720000, 0); in do_firmware_download()
927 status = write_fw_segment(state, seg_address, in do_firmware_download()
933 status = write_fw_segment(state, seg_address, in do_firmware_download()
944 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len) in check_fw() argument
953 dev_info(state->i2cdev, "Invalid FW Header\n"); in check_fw()
960 dev_info(state->i2cdev, "Invalid FW Checksum\n"); in check_fw()
966 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) in firmware_download() argument
974 if (check_fw(state, mbin, mbin_len)) in firmware_download()
978 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0); in firmware_download()
984 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG, in firmware_download()
988 status = write_register(state, HYDRA_RESET_BBAND_REG, in firmware_download()
992 status = write_register(state, HYDRA_RESET_XBAR_REG, in firmware_download()
1000 status = write_register(state, HYDRA_MODULES_CLK_2_REG, in firmware_download()
1005 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data); in firmware_download()
1008 status = do_firmware_download(state, mbin, mbin_len); in firmware_download()
1012 if (state->base->type == MXL_HYDRA_DEVICE_568) { in firmware_download()
1016 status = write_register(state, 0x90720000, 1); in firmware_download()
1022 status = write_register(state, 0x9076B510, 1); in firmware_download()
1027 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1); in firmware_download()
1035 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210); in firmware_download()
1039 if (!firmware_is_alive(state)) in firmware_download()
1042 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n"); in firmware_download()
1049 dev_sku_cfg.sku_type = state->base->sku_type; in firmware_download()
1052 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in firmware_download()
1058 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts) in cfg_ts_pad_mux() argument
1065 if ((state->base->type == MXL_HYDRA_DEVICE_541) || in cfg_ts_pad_mux()
1066 (state->base->type == MXL_HYDRA_DEVICE_541S)) in cfg_ts_pad_mux()
1069 if ((state->base->type == MXL_HYDRA_DEVICE_581) || in cfg_ts_pad_mux()
1070 (state->base->type == MXL_HYDRA_DEVICE_581S)) in cfg_ts_pad_mux()
1076 switch (state->base->type) { in cfg_ts_pad_mux()
1083 status |= update_by_mnemonic(state, 0x90000170, 24, 3, in cfg_ts_pad_mux()
1085 status |= update_by_mnemonic(state, 0x90000170, 28, 3, in cfg_ts_pad_mux()
1087 status |= update_by_mnemonic(state, 0x90000174, 0, 3, in cfg_ts_pad_mux()
1089 status |= update_by_mnemonic(state, 0x90000174, 4, 3, in cfg_ts_pad_mux()
1091 status |= update_by_mnemonic(state, 0x90000174, 8, 3, in cfg_ts_pad_mux()
1093 status |= update_by_mnemonic(state, 0x90000174, 12, 3, in cfg_ts_pad_mux()
1095 status |= update_by_mnemonic(state, 0x90000174, 16, 3, in cfg_ts_pad_mux()
1097 status |= update_by_mnemonic(state, 0x90000174, 20, 3, in cfg_ts_pad_mux()
1099 status |= update_by_mnemonic(state, 0x90000174, 24, 3, in cfg_ts_pad_mux()
1101 status |= update_by_mnemonic(state, 0x90000174, 28, 3, in cfg_ts_pad_mux()
1103 status |= update_by_mnemonic(state, 0x90000178, 0, 3, in cfg_ts_pad_mux()
1105 status |= update_by_mnemonic(state, 0x90000178, 4, 3, in cfg_ts_pad_mux()
1107 status |= update_by_mnemonic(state, 0x90000178, 8, 3, in cfg_ts_pad_mux()
1113 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1); in cfg_ts_pad_mux()
1114 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0); in cfg_ts_pad_mux()
1115 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0); in cfg_ts_pad_mux()
1116 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0); in cfg_ts_pad_mux()
1117 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0); in cfg_ts_pad_mux()
1118 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1); in cfg_ts_pad_mux()
1119 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1); in cfg_ts_pad_mux()
1120 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1); in cfg_ts_pad_mux()
1121 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1); in cfg_ts_pad_mux()
1122 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1); in cfg_ts_pad_mux()
1123 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1); in cfg_ts_pad_mux()
1125 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1127 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1129 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1131 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1133 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1135 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1137 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1139 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1141 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1143 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1145 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1147 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1149 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1151 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1153 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1155 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1157 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1159 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1162 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1164 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1166 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1168 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1170 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1172 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1174 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1176 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1178 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1180 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1182 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1184 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1186 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1188 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1190 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1192 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1194 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1196 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1203 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1205 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1207 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1209 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1211 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1213 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1215 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1217 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1219 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1221 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1223 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1225 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1228 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1230 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1232 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1234 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1236 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1238 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1240 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1242 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1244 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1246 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1248 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1251 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1253 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1255 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1257 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1259 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1261 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1263 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1265 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1268 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1270 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1272 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1274 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1276 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1278 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1280 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1282 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1284 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1286 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1288 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1296 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1298 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1300 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1302 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1304 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1306 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1308 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1310 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1312 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1314 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1316 status |= update_by_mnemonic(state, in cfg_ts_pad_mux()
1323 static int set_drive_strength(struct mxl *state, in set_drive_strength() argument
1329 read_register(state, 0x90000194, &val); in set_drive_strength()
1330 dev_info(state->i2cdev, "DIGIO = %08x\n", val); in set_drive_strength()
1331 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength); in set_drive_strength()
1334 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength); in set_drive_strength()
1335 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength); in set_drive_strength()
1336 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength); in set_drive_strength()
1337 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength); in set_drive_strength()
1338 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength); in set_drive_strength()
1339 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength); in set_drive_strength()
1340 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength); in set_drive_strength()
1341 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength); in set_drive_strength()
1342 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength); in set_drive_strength()
1343 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength); in set_drive_strength()
1344 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength); in set_drive_strength()
1345 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength); in set_drive_strength()
1346 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength); in set_drive_strength()
1347 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength); in set_drive_strength()
1348 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength); in set_drive_strength()
1349 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength); in set_drive_strength()
1350 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength); in set_drive_strength()
1355 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) in enable_tuner() argument
1367 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE, in enable_tuner()
1371 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1374 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1378 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); in enable_tuner()
1379 dev_dbg(state->i2cdev, "tuner %u ready = %u\n", in enable_tuner()
1386 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id, in config_ts() argument
1449 demod_id = state->base->ts_map[demod_id]; in config_ts()
1455 cfg_ts_pad_mux(state, MXL_TRUE); in config_ts()
1456 update_by_mnemonic(state, in config_ts()
1464 if (state->base->chipversion >= 2) { in config_ts()
1465 status |= update_by_mnemonic(state, in config_ts()
1471 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min); in config_ts()
1477 status |= update_by_mnemonic(state, in config_ts()
1483 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type); in config_ts()
1485 status |= update_by_mnemonic(state, in config_ts()
1491 status |= update_by_mnemonic(state, in config_ts()
1497 status |= update_by_mnemonic(state, in config_ts()
1503 status |= update_by_mnemonic(state, in config_ts()
1509 status |= update_by_mnemonic(state, in config_ts()
1515 status |= update_by_mnemonic(state, in config_ts()
1523 status |= update_by_mnemonic(state, in config_ts()
1528 status |= update_by_mnemonic(state, in config_ts()
1536 status |= update_by_mnemonic(state, in config_ts()
1542 status |= update_by_mnemonic(state, in config_ts()
1551 status |= update_by_mnemonic(state, in config_ts()
1557 status |= update_by_mnemonic(state, in config_ts()
1568 status |= update_by_mnemonic(state, in config_ts()
1577 static int config_mux(struct mxl *state) in config_mux() argument
1579 update_by_mnemonic(state, 0x9070000C, 0, 1, 0); in config_mux()
1580 update_by_mnemonic(state, 0x9070000C, 1, 1, 0); in config_mux()
1581 update_by_mnemonic(state, 0x9070000C, 2, 1, 0); in config_mux()
1582 update_by_mnemonic(state, 0x9070000C, 3, 1, 0); in config_mux()
1583 update_by_mnemonic(state, 0x9070000C, 4, 1, 0); in config_mux()
1584 update_by_mnemonic(state, 0x9070000C, 5, 1, 0); in config_mux()
1585 update_by_mnemonic(state, 0x9070000C, 6, 1, 0); in config_mux()
1586 update_by_mnemonic(state, 0x9070000C, 7, 1, 0); in config_mux()
1587 update_by_mnemonic(state, 0x90700008, 0, 2, 1); in config_mux()
1588 update_by_mnemonic(state, 0x90700008, 2, 2, 1); in config_mux()
1592 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) in load_fw() argument
1598 return firmware_download(state, cfg->fw, cfg->fw_len); in load_fw()
1608 stat = firmware_download(state, buf, 0x40000); in load_fw()
1614 static int validate_sku(struct mxl *state) in validate_sku() argument
1618 u32 type = state->base->type; in validate_sku()
1620 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond); in validate_sku()
1621 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id); in validate_sku()
1622 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid); in validate_sku()
1626 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", in validate_sku()
1635 state->base->type = MXL_HYDRA_DEVICE_581; in validate_sku()
1662 static int get_fwinfo(struct mxl *state) in get_fwinfo() argument
1667 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val); in get_fwinfo()
1670 dev_info(state->i2cdev, "chipID=%08x\n", val); in get_fwinfo()
1672 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val); in get_fwinfo()
1675 dev_info(state->i2cdev, "chipVer=%08x\n", val); in get_fwinfo()
1677 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); in get_fwinfo()
1680 dev_info(state->i2cdev, "FWVer=%08x\n", val); in get_fwinfo()
1682 state->base->fwversion = val; in get_fwinfo()
1709 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) in probe() argument
1715 state->base->ts_map = ts_map1_to_1; in probe()
1717 switch (state->base->type) { in probe()
1720 state->base->can_clkout = 1; in probe()
1721 state->base->demod_num = 8; in probe()
1722 state->base->tuner_num = 1; in probe()
1723 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; in probe()
1726 state->base->can_clkout = 1; in probe()
1727 state->base->demod_num = 8; in probe()
1728 state->base->tuner_num = 3; in probe()
1729 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; in probe()
1732 state->base->can_clkout = 0; in probe()
1733 state->base->demod_num = 8; in probe()
1734 state->base->tuner_num = 4; in probe()
1735 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; in probe()
1738 state->base->can_clkout = 0; in probe()
1739 state->base->demod_num = 4; in probe()
1740 state->base->tuner_num = 4; in probe()
1741 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; in probe()
1742 state->base->ts_map = ts_map54x; in probe()
1746 state->base->can_clkout = 0; in probe()
1747 state->base->demod_num = 4; in probe()
1748 state->base->tuner_num = 1; in probe()
1749 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; in probe()
1750 state->base->ts_map = ts_map54x; in probe()
1754 state->base->can_clkout = 0; in probe()
1755 state->base->demod_num = 6; in probe()
1756 state->base->tuner_num = 1; in probe()
1757 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; in probe()
1760 state->base->can_clkout = 0; in probe()
1761 state->base->demod_num = 8; in probe()
1762 state->base->tuner_num = 1; in probe()
1763 state->base->chan_bond = 1; in probe()
1764 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; in probe()
1767 state->base->can_clkout = 1; in probe()
1768 state->base->demod_num = 4; in probe()
1769 state->base->tuner_num = 3; in probe()
1770 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; in probe()
1771 state->base->ts_map = ts_map54x; in probe()
1776 state->base->can_clkout = 0; in probe()
1777 state->base->demod_num = 8; in probe()
1778 state->base->tuner_num = 4; in probe()
1779 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; in probe()
1783 status = validate_sku(state); in probe()
1787 update_by_mnemonic(state, 0x80030014, 9, 1, 1); in probe()
1788 update_by_mnemonic(state, 0x8003003C, 12, 1, 1); in probe()
1789 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver); in probe()
1791 state->base->chipversion = 0; in probe()
1793 state->base->chipversion = (chipver == 2) ? 2 : 1; in probe()
1794 dev_info(state->i2cdev, "Hydra chip version %u\n", in probe()
1795 state->base->chipversion); in probe()
1797 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); in probe()
1799 fw = firmware_is_alive(state); in probe()
1801 status = load_fw(state, cfg); in probe()
1805 get_fwinfo(state); in probe()
1807 config_mux(state); in probe()
1826 for (j = 0; j < state->base->demod_num; j++) { in probe()
1827 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j, in probe()
1832 set_drive_strength(state, 1); in probe()
1840 struct mxl *state; in mxl5xx_attach() local
1843 state = kzalloc(sizeof(struct mxl), GFP_KERNEL); in mxl5xx_attach()
1844 if (!state) in mxl5xx_attach()
1847 state->demod = demod; in mxl5xx_attach()
1848 state->tuner = tuner; in mxl5xx_attach()
1849 state->tuner_in_use = 0xffffffff; in mxl5xx_attach()
1850 state->i2cdev = &i2c->dev; in mxl5xx_attach()
1857 state->base = base; in mxl5xx_attach()
1871 state->base = base; in mxl5xx_attach()
1872 if (probe(state, cfg) < 0) { in mxl5xx_attach()
1878 state->fe.ops = mxl_ops; in mxl5xx_attach()
1879 state->xbar[0] = 4; in mxl5xx_attach()
1880 state->xbar[1] = demod; in mxl5xx_attach()
1881 state->xbar[2] = 8; in mxl5xx_attach()
1882 state->fe.demodulator_priv = state; in mxl5xx_attach()
1885 list_add(&state->mxl, &base->mxls); in mxl5xx_attach()
1886 return &state->fe; in mxl5xx_attach()
1889 kfree(state); in mxl5xx_attach()