213 	u8 r12, r15, r17, r18, r3D, r82, r84, r89;  in mxl111sf_config_pin_mux_modes()  local
239 	ret = mxl111sf_read_reg(state, 0x3D, &r3D);  in mxl111sf_config_pin_mux_modes()
252 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
258 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
280 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
286 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
308 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
314 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
336 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
342 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
364 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
370 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
392 		r3D |= PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
398 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
420 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
426 		r3D |= PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
448 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
454 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
476 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
482 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
505 		r3D &= ~PIN_MUX_MPG_IN_MUX_MASK;  in mxl111sf_config_pin_mux_modes()
511 		r3D &= ~PIN_MUX_SPI_MODE_MASK;  in mxl111sf_config_pin_mux_modes()
548 	ret = mxl111sf_write_reg(state, 0x3D, r3D);  in mxl111sf_config_pin_mux_modes()