Lines Matching refs:ldr
52 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
53 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
56 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
59 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
62 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
65 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
68 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
71 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
74 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
77 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
80 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
83 ldr r1, [r0, #EMIF_COS_CONFIG]
86 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
89 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
92 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
95 ldr r1, [r0, #EMIF_OCP_CONFIG]
98 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
102 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
105 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
108 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
111 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
114 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
117 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
125 ldr r1, [r3, r5]
144 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
145 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
148 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
152 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
156 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
160 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
164 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
168 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
171 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
174 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
177 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
180 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
183 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
186 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
189 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
193 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
196 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
199 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
202 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
205 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
208 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
211 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
222 ldr r1, [r3, r5]
235 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
239 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
258 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
259 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
261 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
278 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
279 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
289 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
297 1: ldr r1, [r0, #EMIF_STATUS]
315 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
316 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
318 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
323 1: ldr r1, [r0, #EMIF_STATUS]