154 static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)  in csr_readl()  function
161 	return (csr_readl(pcie, LTSSM_STATUS) &  in mobiveil_pcie_link_up()
238 	val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
239 	mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_pcie_isr()
244 		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>  in mobiveil_pcie_isr()
365 	pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);  in select_paged_register()
388 	return csr_readl(pcie, off);  in read_paged_register()
404 	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);  in program_ib_windows()
443 	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));  in program_ob_windows()
454 	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));  in program_ob_windows()
458 	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));  in program_ob_windows()
512 	value = csr_readl(pcie, PCI_PRIMARY_BUS);  in mobiveil_host_init()
521 	value = csr_readl(pcie, PCI_COMMAND);  in mobiveil_host_init()
529 	pab_ctrl = csr_readl(pcie, PAB_CTRL);  in mobiveil_host_init()
540 	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
575 	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
596 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
611 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()