148 static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,  in csr_writel()  function
206 	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |  in mobiveil_pcie_map_bus()
257 				csr_writel(pcie,  in mobiveil_pcie_isr()
294 	csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
371 	csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);  in select_paged_register()
380 	csr_writel(pcie, val, off);  in write_paged_register()
405 	csr_writel(pcie,  in program_ib_windows()
444 	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |  in program_ob_windows()
455 	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),  in program_ob_windows()
460 	csr_writel(pcie, lower_32_bits(pci_addr),  in program_ob_windows()
462 	csr_writel(pcie, upper_32_bits(pci_addr),  in program_ob_windows()
515 	csr_writel(pcie, value, PCI_PRIMARY_BUS);  in mobiveil_host_init()
522 	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |  in mobiveil_host_init()
530 	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |  in mobiveil_host_init()
533 	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),  in mobiveil_host_init()
541 	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
578 	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
597 	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
612 	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()