148 static inline void csr_writel(struct mobiveil_pcie *pcie, const u32 value,  in csr_writel()  argument
151 	writel_relaxed(value, pcie->csr_axi_slave_base + reg);  in csr_writel()
154 static inline u32 csr_readl(struct mobiveil_pcie *pcie, const u32 reg)  in csr_readl()  argument
156 	return readl_relaxed(pcie->csr_axi_slave_base + reg);  in csr_readl()
159 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  in mobiveil_pcie_link_up()  argument
161 	return (csr_readl(pcie, LTSSM_STATUS) &  in mobiveil_pcie_link_up()
167 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_valid_device()  local
170 	if ((bus->number == pcie->root_bus_nr) && (devfn > 0))  in mobiveil_pcie_valid_device()
177 	if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))  in mobiveil_pcie_valid_device()
190 	struct mobiveil_pcie *pcie = bus->sysdata;  in mobiveil_pcie_map_bus()  local
195 	if (bus->number == pcie->root_bus_nr) {  in mobiveil_pcie_map_bus()
197 		return pcie->csr_axi_slave_base + where;  in mobiveil_pcie_map_bus()
206 	csr_writel(pcie, bus->number << PAB_BUS_SHIFT |  in mobiveil_pcie_map_bus()
210 	return pcie->config_axi_slave_base + where;  in mobiveil_pcie_map_bus()
222 	struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);  in mobiveil_pcie_isr()  local
223 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_isr()
224 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_pcie_isr()
238 	val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
239 	mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_pcie_isr()
244 		shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT) >>  in mobiveil_pcie_isr()
248 				virq = irq_find_mapping(pcie->intx_domain,  in mobiveil_pcie_isr()
257 				csr_writel(pcie,  in mobiveil_pcie_isr()
265 	msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);  in mobiveil_pcie_isr()
269 		msi_data = readl_relaxed(pcie->apb_csr_base  in mobiveil_pcie_isr()
278 		msi_addr_lo = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
280 		msi_addr_hi = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
289 		msi_status = readl_relaxed(pcie->apb_csr_base +  in mobiveil_pcie_isr()
294 	csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);  in mobiveil_pcie_isr()
298 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)  in mobiveil_pcie_parse_dt()  argument
300 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_parse_dt()
301 	struct platform_device *pdev = pcie->pdev;  in mobiveil_pcie_parse_dt()
315 	pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
316 	if (IS_ERR(pcie->config_axi_slave_base))  in mobiveil_pcie_parse_dt()
317 		return PTR_ERR(pcie->config_axi_slave_base);  in mobiveil_pcie_parse_dt()
318 	pcie->ob_io_res = res;  in mobiveil_pcie_parse_dt()
323 	pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
324 	if (IS_ERR(pcie->csr_axi_slave_base))  in mobiveil_pcie_parse_dt()
325 		return PTR_ERR(pcie->csr_axi_slave_base);  in mobiveil_pcie_parse_dt()
326 	pcie->pcie_reg_base = res->start;  in mobiveil_pcie_parse_dt()
330 	pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);  in mobiveil_pcie_parse_dt()
331 	if (IS_ERR(pcie->apb_csr_base))  in mobiveil_pcie_parse_dt()
332 		return PTR_ERR(pcie->apb_csr_base);  in mobiveil_pcie_parse_dt()
335 	if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))  in mobiveil_pcie_parse_dt()
336 		pcie->apio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
338 	if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))  in mobiveil_pcie_parse_dt()
339 		pcie->ppio_wins = MAX_PIO_WINDOWS;  in mobiveil_pcie_parse_dt()
341 	pcie->irq = platform_get_irq(pdev, 0);  in mobiveil_pcie_parse_dt()
342 	if (pcie->irq <= 0) {  in mobiveil_pcie_parse_dt()
343 		dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);  in mobiveil_pcie_parse_dt()
347 	irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);  in mobiveil_pcie_parse_dt()
360 static void select_paged_register(struct mobiveil_pcie *pcie, u32 offset)  in select_paged_register()  argument
365 	pab_ctrl_dw = csr_readl(pcie, PAB_CTRL);  in select_paged_register()
371 	csr_writel(pcie, pab_ctrl_dw, PAB_CTRL);  in select_paged_register()
374 static void write_paged_register(struct mobiveil_pcie *pcie,  in write_paged_register()  argument
379 	select_paged_register(pcie, offset);  in write_paged_register()
380 	csr_writel(pcie, val, off);  in write_paged_register()
383 static u32 read_paged_register(struct mobiveil_pcie *pcie, u32 offset)  in read_paged_register()  argument
387 	select_paged_register(pcie, offset);  in read_paged_register()
388 	return csr_readl(pcie, off);  in read_paged_register()
391 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,  in program_ib_windows()  argument
398 	if (win_num >= pcie->ppio_wins) {  in program_ib_windows()
399 		dev_err(&pcie->pdev->dev,  in program_ib_windows()
404 	pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);  in program_ib_windows()
405 	csr_writel(pcie,  in program_ib_windows()
407 	amap_ctrl_dw = read_paged_register(pcie, PAB_PEX_AMAP_CTRL(win_num));  in program_ib_windows()
411 	write_paged_register(pcie, amap_ctrl_dw | lower_32_bits(size64),  in program_ib_windows()
414 	write_paged_register(pcie, upper_32_bits(size64),  in program_ib_windows()
417 	write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));  in program_ib_windows()
418 	write_paged_register(pcie, pci_addr, PAB_PEX_AMAP_PEX_WIN_L(win_num));  in program_ib_windows()
419 	write_paged_register(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));  in program_ib_windows()
425 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,  in program_ob_windows()  argument
432 	if (win_num >= pcie->apio_wins) {  in program_ob_windows()
433 		dev_err(&pcie->pdev->dev,  in program_ob_windows()
443 	value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));  in program_ob_windows()
444 	csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |  in program_ob_windows()
447 	write_paged_register(pcie, upper_32_bits(size64),  in program_ob_windows()
454 	value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));  in program_ob_windows()
455 	csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),  in program_ob_windows()
458 	value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));  in program_ob_windows()
460 	csr_writel(pcie, lower_32_bits(pci_addr),  in program_ob_windows()
462 	csr_writel(pcie, upper_32_bits(pci_addr),  in program_ob_windows()
465 	pcie->ob_wins_configured++;  in program_ob_windows()
468 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)  in mobiveil_bringup_link()  argument
474 		if (mobiveil_pcie_link_up(pcie))  in mobiveil_bringup_link()
479 	dev_err(&pcie->pdev->dev, "link never came up\n");  in mobiveil_bringup_link()
483 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)  in mobiveil_pcie_enable_msi()  argument
485 	phys_addr_t msg_addr = pcie->pcie_reg_base;  in mobiveil_pcie_enable_msi()
486 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_pcie_enable_msi()
488 	pcie->msi.num_of_vectors = PCI_NUM_MSI;  in mobiveil_pcie_enable_msi()
492 		pcie->apb_csr_base + MSI_BASE_LO_OFFSET);  in mobiveil_pcie_enable_msi()
494 		pcie->apb_csr_base + MSI_BASE_HI_OFFSET);  in mobiveil_pcie_enable_msi()
495 	writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);  in mobiveil_pcie_enable_msi()
496 	writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);  in mobiveil_pcie_enable_msi()
499 static int mobiveil_host_init(struct mobiveil_pcie *pcie)  in mobiveil_host_init()  argument
505 	err = mobiveil_bringup_link(pcie);  in mobiveil_host_init()
507 		dev_info(&pcie->pdev->dev, "link bring-up failed\n");  in mobiveil_host_init()
512 	value = csr_readl(pcie, PCI_PRIMARY_BUS);  in mobiveil_host_init()
515 	csr_writel(pcie, value, PCI_PRIMARY_BUS);  in mobiveil_host_init()
521 	value = csr_readl(pcie, PCI_COMMAND);  in mobiveil_host_init()
522 	csr_writel(pcie, value | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |  in mobiveil_host_init()
529 	pab_ctrl = csr_readl(pcie, PAB_CTRL);  in mobiveil_host_init()
530 	csr_writel(pcie, pab_ctrl | (1 << AMBA_PIO_ENABLE_SHIFT) |  in mobiveil_host_init()
533 	csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),  in mobiveil_host_init()
540 	value = csr_readl(pcie, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
541 	csr_writel(pcie, value | APIO_EN_MASK, PAB_AXI_PIO_CTRL);  in mobiveil_host_init()
551 	program_ob_windows(pcie, pcie->ob_wins_configured,  in mobiveil_host_init()
552 			pcie->ob_io_res->start, 0, CFG_WINDOW_TYPE,  in mobiveil_host_init()
553 			resource_size(pcie->ob_io_res));  in mobiveil_host_init()
556 	program_ib_windows(pcie, WIN_NUM_0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);  in mobiveil_host_init()
559 	resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {  in mobiveil_host_init()
567 			program_ob_windows(pcie, pcie->ob_wins_configured,  in mobiveil_host_init()
575 	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
578 	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);  in mobiveil_host_init()
581 	mobiveil_pcie_enable_msi(pcie);  in mobiveil_host_init()
589 	struct mobiveil_pcie *pcie;  in mobiveil_mask_intx_irq()  local
593 	pcie = irq_desc_get_chip_data(desc);  in mobiveil_mask_intx_irq()
595 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
596 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
597 	csr_writel(pcie, (shifted_val & (~mask)), PAB_INTP_AMBA_MISC_ENB);  in mobiveil_mask_intx_irq()
598 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  in mobiveil_mask_intx_irq()
604 	struct mobiveil_pcie *pcie;  in mobiveil_unmask_intx_irq()  local
608 	pcie = irq_desc_get_chip_data(desc);  in mobiveil_unmask_intx_irq()
610 	raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
611 	shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
612 	csr_writel(pcie, (shifted_val | mask), PAB_INTP_AMBA_MISC_ENB);  in mobiveil_unmask_intx_irq()
613 	raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);  in mobiveil_unmask_intx_irq()
652 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);  in mobiveil_compose_msi_msg()  local
653 	phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));  in mobiveil_compose_msi_msg()
659 	dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",  in mobiveil_compose_msi_msg()
678 	struct mobiveil_pcie *pcie = domain->host_data;  in mobiveil_irq_msi_domain_alloc()  local
679 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_irq_msi_domain_alloc()
705 	struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);  in mobiveil_irq_msi_domain_free()  local
706 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_irq_msi_domain_free()
711 		dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",  in mobiveil_irq_msi_domain_free()
724 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)  in mobiveil_allocate_msi_domains()  argument
726 	struct device *dev = &pcie->pdev->dev;  in mobiveil_allocate_msi_domains()
728 	struct mobiveil_msi *msi = &pcie->msi;  in mobiveil_allocate_msi_domains()
730 	mutex_init(&pcie->msi.lock);  in mobiveil_allocate_msi_domains()
732 						&msi_domain_ops, pcie);  in mobiveil_allocate_msi_domains()
748 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)  in mobiveil_pcie_init_irq_domain()  argument
750 	struct device *dev = &pcie->pdev->dev;  in mobiveil_pcie_init_irq_domain()
755 	pcie->intx_domain = irq_domain_add_linear(node,  in mobiveil_pcie_init_irq_domain()
756 				PCI_NUM_INTX, &intx_domain_ops, pcie);  in mobiveil_pcie_init_irq_domain()
758 	if (!pcie->intx_domain) {  in mobiveil_pcie_init_irq_domain()
763 	raw_spin_lock_init(&pcie->intx_mask_lock);  in mobiveil_pcie_init_irq_domain()
766 	ret = mobiveil_allocate_msi_domains(pcie);  in mobiveil_pcie_init_irq_domain()
775 	struct mobiveil_pcie *pcie;  in mobiveil_pcie_probe()  local
784 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in mobiveil_pcie_probe()
788 	pcie = pci_host_bridge_priv(bridge);  in mobiveil_pcie_probe()
789 	if (!pcie)  in mobiveil_pcie_probe()
792 	pcie->pdev = pdev;  in mobiveil_pcie_probe()
794 	ret = mobiveil_pcie_parse_dt(pcie);  in mobiveil_pcie_probe()
800 	INIT_LIST_HEAD(&pcie->resources);  in mobiveil_pcie_probe()
804 						    &pcie->resources, &iobase);  in mobiveil_pcie_probe()
814 	ret = mobiveil_host_init(pcie);  in mobiveil_pcie_probe()
821 	ret = mobiveil_pcie_init_irq_domain(pcie);  in mobiveil_pcie_probe()
827 	ret = devm_request_pci_bus_resources(dev, &pcie->resources);  in mobiveil_pcie_probe()
832 	list_splice_init(&pcie->resources, &bridge->windows);  in mobiveil_pcie_probe()
834 	bridge->sysdata = pcie;  in mobiveil_pcie_probe()
835 	bridge->busnr = pcie->root_bus_nr;  in mobiveil_pcie_probe()
854 	pci_free_resource_list(&pcie->resources);  in mobiveil_pcie_probe()