Lines Matching defs:mlx4_caps
533 struct mlx4_caps { struct
534 u64 fw_ver;
535 u32 function;
536 int num_ports;
537 int vl_cap[MLX4_MAX_PORTS + 1];
538 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
539 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
540 u64 def_mac[MLX4_MAX_PORTS + 1];
541 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
542 int gid_table_len[MLX4_MAX_PORTS + 1];
543 int pkey_table_len[MLX4_MAX_PORTS + 1];
544 int trans_type[MLX4_MAX_PORTS + 1];
545 int vendor_oui[MLX4_MAX_PORTS + 1];
546 int wavelength[MLX4_MAX_PORTS + 1];
547 u64 trans_code[MLX4_MAX_PORTS + 1];
548 int local_ca_ack_delay;
549 int num_uars;
550 u32 uar_page_size;
551 int bf_reg_size;
552 int bf_regs_per_page;
553 int max_sq_sg;
554 int max_rq_sg;
555 int num_qps;
556 int max_wqes;
557 int max_sq_desc_sz;
558 int max_rq_desc_sz;
559 int max_qp_init_rdma;
560 int max_qp_dest_rdma;
561 int max_tc_eth;
562 struct mlx4_spec_qps *spec_qps;
563 int num_srqs;
564 int max_srq_wqes;
565 int max_srq_sge;
566 int reserved_srqs;
567 int num_cqs;
568 int max_cqes;
569 int reserved_cqs;
570 int num_sys_eqs;
571 int num_eqs;
572 int reserved_eqs;
573 int num_comp_vectors;
574 int num_mpts;
575 int max_fmr_maps;
576 int num_mtts;
577 int fmr_reserved_mtts;
578 int reserved_mtts;
579 int reserved_mrws;
580 int reserved_uars;
581 int num_mgms;
582 int num_amgms;
583 int reserved_mcgs;
584 int num_qp_per_mgm;
585 int steering_mode;
586 int dmfs_high_steer_mode;
587 int fs_log_max_ucast_qp_range_size;
588 int num_pds;
589 int reserved_pds;
590 int max_xrcds;
591 int reserved_xrcds;
592 int mtt_entry_sz;
593 u32 max_msg_sz;
594 u32 page_size_cap;
595 u64 flags;
596 u64 flags2;
597 u32 bmme_flags;
598 u32 reserved_lkey;
599 u16 stat_rate_support;
600 u8 port_width_cap[MLX4_MAX_PORTS + 1];
601 int max_gso_sz;
602 int max_rss_tbl_sz;
603 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
604 int reserved_qps;
605 int reserved_qps_base[MLX4_NUM_QP_REGION];
606 int log_num_macs;
607 int log_num_vlans;
608 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
609 u8 supported_type[MLX4_MAX_PORTS + 1];
610 u8 suggested_type[MLX4_MAX_PORTS + 1];
611 u8 default_sense[MLX4_MAX_PORTS + 1];
612 u32 port_mask[MLX4_MAX_PORTS + 1];
613 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
614 u32 max_counters;
615 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
616 u16 sqp_demux;
617 u32 eqe_size;
618 u32 cqe_size;
619 u8 eqe_factor;
620 u32 userspace_caps; /* userspace must be aware of these */
621 u32 function_caps; /* VFs must be aware of these */
622 u16 hca_core_clock;
623 u64 phys_port_id[MLX4_MAX_PORTS + 1];
624 int tunnel_offload_mode;
625 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
626 u8 phv_bit[MLX4_MAX_PORTS + 1];
627 u8 alloc_res_qp_mask;
628 u32 dmfs_high_rate_qpn_base;
629 u32 dmfs_high_rate_qpn_range;
630 u32 vf_caps;
631 bool wol_port[MLX4_MAX_PORTS + 1];
632 struct mlx4_rate_limit_caps rl_caps;
633 u32 health_buffer_addrs;
634 bool map_clock_to_user;