Lines Matching defs:mactx_phy_desc
36 struct mactx_phy_desc { struct
38 uint32_t reserved_0a : 16, // [15:0]
39 bf_type : 2, // [17:16]
40 wait_sifs : 2, // [19:18]
41 dot11b_preamble_type : 1, // [20:20]
42 pkt_type : 4, // [24:21]
43 su_or_mu : 2, // [26:25]
44 mu_type : 1, // [27:27]
45 bandwidth : 3, // [30:28]
46 channel_capture : 1; // [31:31]
47 uint32_t mcs : 4, // [3:0]
48 global_ofdma_mimo_enable : 1, // [4:4]
49 reserved_1a : 1, // [5:5]
50 stbc : 1, // [6:6]
51 dot11ax_su_extended : 1, // [7:7]
52 dot11ax_trigger_frame_embedded : 1, // [8:8]
53 tx_pwr_shared : 8, // [16:9]
54 tx_pwr_unshared : 8, // [24:17]
55 measure_power : 1, // [25:25]
56 tpc_glut_self_cal : 1, // [26:26]
57 back_to_back_transmission_expected : 1, // [27:27]
58 heavy_clip_nss : 3, // [30:28]
59 txbf_per_packet_no_csd_no_walsh : 1; // [31:31]
60 uint32_t ndp : 2, // [1:0]
61 ul_flag : 1, // [2:2]
62 triggered : 1, // [3:3]
63 ap_pkt_bw : 3, // [6:4]
64 ru_position_start : 8, // [14:7]
65 pcu_ppdu_setup_start_reason : 3, // [17:15]
66 tlv_source : 1, // [18:18]
67 reserved_2a : 2, // [20:19]
68 nss : 3, // [23:21]
69 stream_offset : 3, // [26:24]
70 reserved_2b : 2, // [28:27]
71 clpc_enable : 1, // [29:29]
72 mu_ndp : 1, // [30:30]
73 response_expected : 1; // [31:31]
74 uint32_t rx_chain_mask : 8, // [7:0]
75 rx_chain_mask_valid : 1, // [8:8]
76 ant_sel_valid : 1, // [9:9]
77 ant_sel : 1, // [10:10]
78 cp_setting : 2, // [12:11]
79 he_ppdu_subtype : 2, // [14:13]
80 active_channel : 3, // [17:15]
81 generate_phyrx_tx_start_timing : 1, // [18:18]
82 ltf_size : 2, // [20:19]
83 ru_size_updated_v2 : 4, // [24:21]
84 reserved_3c : 1, // [25:25]
85 u_sig_puncture_pattern_encoding : 6; // [31:26]