Lines Matching defs:mask
52 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ argument
56 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ argument
140 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ argument
144 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ argument
183 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ argument
187 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ argument
226 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ argument
230 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ argument
269 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ argument
273 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ argument
312 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ argument
316 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ argument
355 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ argument
359 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ argument
398 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ argument
402 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ argument
441 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ argument
445 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ argument
484 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ argument
488 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ argument
506 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ argument
510 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ argument
549 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ argument
553 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ argument
592 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ argument
596 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ argument
617 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ argument
621 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ argument
639 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ argument
643 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ argument
664 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ argument
668 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ argument
686 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ argument
690 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ argument
711 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ argument
715 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ argument
763 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ argument
767 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
785 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ argument
789 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
807 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
811 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
835 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
839 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
857 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
861 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
885 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
889 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
907 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
911 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
929 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
933 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
954 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
958 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
976 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
980 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
1001 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ argument
1005 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1023 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1027 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1045 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask) \ argument
1049 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1067 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask) \ argument
1071 #define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1092 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask) \ argument
1096 #define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val) \ argument
1114 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask) \ argument
1118 #define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val) \ argument
1139 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask) \ argument
1143 #define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val) \ argument
1191 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ argument
1195 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
1213 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ argument
1217 #define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
1235 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
1239 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
1263 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
1267 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
1285 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
1289 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
1313 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
1317 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
1335 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
1339 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
1357 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
1361 #define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
1382 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
1386 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
1404 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
1408 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
1429 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask) \ argument
1433 #define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1451 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1455 #define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1473 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask) \ argument
1477 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1495 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask) \ argument
1499 #define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1520 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask) \ argument
1524 #define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val) \ argument
1542 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask) \ argument
1546 #define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val) \ argument
1567 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask) \ argument
1571 #define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val) \ argument
1619 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask) \ argument
1623 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
1641 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask) \ argument
1645 #define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
1663 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
1667 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
1691 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
1695 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
1713 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
1717 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
1741 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
1745 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
1763 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
1767 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
1785 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
1789 #define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
1810 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
1814 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
1832 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
1836 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
1857 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask) \ argument
1861 #define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1879 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1883 #define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1901 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ argument
1905 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1923 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ argument
1927 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1948 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ argument
1952 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ argument
1970 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ argument
1974 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ argument
1995 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ argument
1999 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ argument
2047 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ argument
2051 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
2069 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ argument
2073 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
2091 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
2095 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
2119 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
2123 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
2141 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
2145 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
2169 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
2173 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
2191 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
2195 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
2213 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
2217 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
2238 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
2242 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
2260 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ argument
2264 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ argument
2282 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ argument
2286 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ argument
2307 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ argument
2311 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ argument
2329 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ argument
2333 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ argument
2354 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ argument
2358 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ argument
2406 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ argument
2410 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
2428 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ argument
2432 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
2450 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
2454 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
2478 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
2482 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
2500 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
2504 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
2528 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
2532 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
2550 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
2554 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
2572 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
2576 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
2597 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
2601 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
2619 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
2623 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
2644 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ argument
2648 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
2666 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
2670 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
2688 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ argument
2692 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ argument
2710 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ argument
2714 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ argument
2735 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ argument
2739 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ argument
2757 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ argument
2761 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ argument
2782 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ argument
2786 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ argument
2834 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ argument
2838 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
2856 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ argument
2860 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
2878 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
2882 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
2906 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
2910 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
2928 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
2932 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
2956 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
2960 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
2978 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
2982 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
3000 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
3004 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
3025 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3029 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3047 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3051 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3072 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ argument
3076 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3094 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3098 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3116 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ argument
3120 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3138 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ argument
3142 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3163 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ argument
3167 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ argument
3188 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ argument
3192 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ argument
3213 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ argument
3217 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ argument
3268 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ argument
3272 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
3290 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ argument
3294 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
3312 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
3316 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
3340 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
3344 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
3368 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
3372 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
3390 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3394 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3412 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3416 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3437 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ argument
3441 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3459 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3463 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3481 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ argument
3485 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3503 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ argument
3507 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3528 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ argument
3532 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ argument
3553 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ argument
3557 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ argument
3578 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ argument
3582 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ argument
3633 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ argument
3637 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
3655 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ argument
3659 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
3677 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
3681 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
3705 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
3709 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
3733 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
3737 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
3755 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3759 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3777 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3781 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3802 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ argument
3806 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3824 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3828 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3846 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ argument
3850 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3868 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ argument
3872 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3893 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ argument
3897 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ argument
3918 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ argument
3922 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ argument
3943 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ argument
3947 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ argument
3998 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4002 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4020 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4024 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4042 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4046 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4070 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4074 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4098 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4102 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4120 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4124 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4142 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4146 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4167 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ argument
4171 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4189 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4193 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4211 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ argument
4215 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4233 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ argument
4237 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4258 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ argument
4262 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ argument
4283 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ argument
4287 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ argument
4308 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ argument
4312 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ argument
4363 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4367 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4385 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4389 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4407 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4411 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4435 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4439 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4463 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4467 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4485 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4489 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4507 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4511 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4532 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ argument
4536 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4554 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4558 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4576 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, mask) \ argument
4580 #define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4598 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, mask) \ argument
4602 #define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4623 #define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, mask) \ argument
4627 #define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x, mask, val) \ argument
4648 #define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, mask) \ argument
4652 #define HWIO_REO_R0_REO2SW5_RING_STATUS_OUTM(x, mask, val) \ argument
4673 #define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, mask) \ argument
4677 #define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x, mask, val) \ argument
4728 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4732 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4750 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4754 #define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4772 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4776 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4800 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4804 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4828 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4832 #define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4850 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4854 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4872 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4876 #define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4897 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, mask) \ argument
4901 #define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4919 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4923 #define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4941 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, mask) \ argument
4945 #define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4963 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, mask) \ argument
4967 #define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4988 #define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, mask) \ argument
4992 #define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x, mask, val) \ argument
5013 #define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, mask) \ argument
5017 #define HWIO_REO_R0_REO2SW6_RING_STATUS_OUTM(x, mask, val) \ argument
5038 #define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, mask) \ argument
5042 #define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x, mask, val) \ argument
5093 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, mask) \ argument
5097 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
5115 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, mask) \ argument
5119 #define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
5137 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
5141 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
5165 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
5169 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
5193 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
5197 #define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
5215 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
5219 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
5237 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
5241 #define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
5262 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, mask) \ argument
5266 #define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
5284 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
5288 #define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
5306 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ argument
5310 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ argument
5328 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ argument
5332 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ argument
5353 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ argument
5357 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ argument
5378 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ argument
5382 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ argument
5403 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ argument
5407 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ argument
5458 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ argument
5462 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
5480 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ argument
5484 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
5502 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
5506 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
5530 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
5534 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
5558 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
5562 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
5580 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
5584 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
5602 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
5606 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
5627 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ argument
5631 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
5649 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
5653 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
5671 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ argument
5675 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ argument
5693 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ argument
5697 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ argument
5718 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ argument
5722 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ argument
5743 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ argument
5747 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ argument
5768 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ argument
5772 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ argument
5823 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ argument
5827 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
5845 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ argument
5849 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
5867 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
5871 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
5895 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
5899 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
5923 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
5927 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
5945 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
5949 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
5967 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
5971 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
5992 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ argument
5996 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
6014 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
6018 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
6036 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ argument
6040 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ argument
6058 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ argument
6062 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ argument
6083 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ argument
6087 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ argument
6108 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ argument
6112 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ argument
6133 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ argument
6137 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ argument
6188 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ argument
6192 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
6210 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ argument
6214 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
6232 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
6236 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
6260 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
6264 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
6288 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
6292 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
6310 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
6314 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
6332 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ argument
6336 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ argument
6354 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ argument
6358 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ argument
6379 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ argument
6383 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ argument
6404 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ argument
6408 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ argument
6429 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ argument
6433 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ argument
6484 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ argument
6488 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
6506 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ argument
6510 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
6528 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
6532 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
6556 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
6560 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
6584 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
6588 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
6606 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
6610 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
6628 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
6632 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
6653 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ argument
6657 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
6675 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
6679 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
6697 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ argument
6701 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ argument
6722 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ argument
6726 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ argument
6744 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ argument
6748 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ argument
6766 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ argument
6770 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ argument
6788 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ argument
6792 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ argument
6810 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ argument
6814 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ argument
6832 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ argument
6836 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ argument
6854 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ argument
6858 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ argument
6876 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ argument
6880 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ argument
6898 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ argument
6902 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ argument
6920 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ argument
6924 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ argument
6942 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ argument
6946 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ argument
6964 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ argument
6968 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ argument
6986 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ argument
6990 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ argument
7008 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ argument
7012 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ argument
7030 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ argument
7034 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ argument
7052 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ argument
7056 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ argument
7074 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ argument
7078 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ argument
7096 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ argument
7100 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ argument
7118 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ argument
7122 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ argument
7140 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ argument
7144 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ argument
7162 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ argument
7166 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ argument
7184 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ argument
7188 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ argument
7206 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ argument
7210 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ argument
7228 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ argument
7232 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ argument
7250 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ argument
7254 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ argument
7272 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ argument
7276 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ argument
7294 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ argument
7298 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ argument
7316 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ argument
7320 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ argument
7338 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ argument
7342 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ argument
7360 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ argument
7364 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ argument
7382 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ argument
7386 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ argument
7410 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ argument
7414 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ argument
7432 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ argument
7436 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ argument
7454 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ argument
7458 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ argument
7476 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ argument
7480 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ argument
7498 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ argument
7502 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ argument
7520 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ argument
7524 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ argument
7542 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ argument
7546 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ argument
7564 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ argument
7568 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ argument
7586 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ argument
7590 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ argument
7608 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ argument
7612 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ argument
7630 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ argument
7634 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ argument
7652 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ argument
7656 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ argument
7674 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ argument
7678 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ argument
7696 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ argument
7700 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ argument
7718 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ argument
7722 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ argument
7740 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ argument
7744 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ argument
7762 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ argument
7766 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ argument
7784 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ argument
7788 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ argument
7806 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ argument
7810 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ argument
7828 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ argument
7832 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ argument
7850 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ argument
7854 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ argument
7872 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ argument
7876 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ argument
7897 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
7901 #define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
7922 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
7926 #define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
7947 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
7951 #define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
7972 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
7976 #define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
7997 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
8001 #define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
8022 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
8026 #define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
8047 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
8051 #define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
8072 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ argument
8076 #define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ argument
8097 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ argument
8101 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ argument
8119 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ argument
8123 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ argument
8141 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ argument
8145 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ argument
8169 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ argument
8173 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
8191 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ argument
8195 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ argument
8249 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ argument
8253 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ argument
8280 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ argument
8284 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ argument
8308 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ argument
8312 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ argument
8339 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ argument
8343 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ argument
8370 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ argument
8374 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ argument
8419 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ argument
8423 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ argument
8444 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ argument
8448 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ argument
8466 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ argument
8470 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ argument
8491 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ argument
8495 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ argument
8519 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ argument
8523 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ argument
8547 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ argument
8551 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ argument
8569 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ argument
8573 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ argument
8591 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ argument
8595 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ argument
8613 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ argument
8617 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ argument
8635 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ argument
8639 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ argument
8684 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ argument
8688 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ argument
8706 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ argument
8710 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ argument
8755 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ argument
8759 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ argument
8777 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ argument
8781 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ argument
8799 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ argument
8803 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ argument
8821 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ argument
8825 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ argument
8843 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ argument
8847 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ argument
8877 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ argument
8881 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ argument
8902 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ argument
8906 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ argument
8933 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ argument
8937 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ argument
8955 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ argument
8959 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ argument
8977 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ argument
8981 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ argument
8999 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ argument
9003 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ argument
9021 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ argument
9025 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ argument
9043 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ argument
9047 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ argument
9074 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ argument
9078 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
9096 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ argument
9100 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ argument
9118 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ argument
9122 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ argument
9140 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ argument
9144 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
9162 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ argument
9166 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ argument
9190 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ argument
9194 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ argument
9212 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ argument
9216 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ argument
9234 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ argument
9238 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ argument
9256 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ argument
9260 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ argument
9278 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ argument
9282 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ argument
9300 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ argument
9304 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ argument
9322 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ argument
9326 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ argument
9344 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ argument
9348 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ argument
9366 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ argument
9370 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ argument
9388 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ argument
9392 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ argument
9410 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ argument
9414 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ argument
9432 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ argument
9436 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ argument
9457 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ argument
9461 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ argument
9479 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ argument
9483 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ argument
9501 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask) \ argument
9505 #define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val) \ argument
9523 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask) \ argument
9527 #define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val) \ argument
9545 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask) \ argument
9549 #define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val) \ argument
9567 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask) \ argument
9571 #define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val) \ argument
9589 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ argument
9593 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ argument
9611 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ argument
9615 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ argument
9633 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ argument
9637 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ argument
9655 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ argument
9659 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ argument
9677 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ argument
9681 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ argument
9699 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ argument
9703 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ argument
9721 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ argument
9725 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ argument
9743 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ argument
9747 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ argument
9765 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ argument
9769 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ argument
9787 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ argument
9791 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ argument
9809 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ argument
9813 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ argument
9831 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ argument
9835 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ argument
9853 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ argument
9857 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ argument
9875 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ argument
9879 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ argument
9897 #define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, mask) \ argument
9901 #define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x, mask, val) \ argument
9919 #define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, mask) \ argument
9923 #define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x, mask, val) \ argument
9941 #define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, mask) \ argument
9945 #define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x, mask, val) \ argument
9963 #define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, mask) \ argument
9967 #define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x, mask, val) \ argument
9985 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ argument
9989 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ argument
10007 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ argument
10011 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ argument
10029 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ argument
10033 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ argument
10051 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ argument
10055 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ argument
10073 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ argument
10077 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ argument
10095 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ argument
10099 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ argument
10117 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ argument
10121 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ argument
10139 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ argument
10143 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ argument