Lines Matching defs:mask
41 #define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ argument
45 #define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ argument
132 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ argument
136 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ argument
175 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ argument
179 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ argument
218 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ argument
222 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ argument
261 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ argument
265 #define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ argument
304 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ argument
308 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ argument
347 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ argument
351 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ argument
390 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ argument
394 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ argument
433 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ argument
437 #define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ argument
476 #define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ argument
480 #define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ argument
498 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ argument
502 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ argument
541 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ argument
545 #define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ argument
584 #define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ argument
588 #define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ argument
609 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ argument
613 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ argument
631 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ argument
635 #define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ argument
656 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ argument
660 #define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ argument
678 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ argument
682 #define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ argument
703 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ argument
707 #define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ argument
755 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ argument
759 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
777 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ argument
781 #define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
799 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
803 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
827 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
831 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
849 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
853 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
877 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
881 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
899 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
903 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
921 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
925 #define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
946 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
950 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
968 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
972 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
993 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ argument
997 #define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1015 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1019 #define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1037 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ argument
1041 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1059 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ argument
1063 #define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1084 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ argument
1088 #define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ argument
1106 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ argument
1110 #define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ argument
1131 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ argument
1135 #define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ argument
1183 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ argument
1187 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
1205 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ argument
1209 #define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
1227 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
1231 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
1255 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
1259 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
1277 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
1281 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
1305 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
1309 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
1327 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
1331 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
1349 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
1353 #define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
1374 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
1378 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
1396 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
1400 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
1421 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ argument
1425 #define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1443 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1447 #define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1465 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ argument
1469 #define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1487 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ argument
1491 #define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1512 #define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ argument
1516 #define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ argument
1534 #define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ argument
1538 #define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ argument
1559 #define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ argument
1563 #define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ argument
1611 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ argument
1615 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
1633 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ argument
1637 #define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
1655 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
1659 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
1683 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
1687 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
1705 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
1709 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
1733 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
1737 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
1755 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
1759 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
1777 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
1781 #define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
1802 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
1806 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
1824 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
1828 #define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
1849 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ argument
1853 #define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
1871 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
1875 #define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
1893 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ argument
1897 #define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ argument
1915 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ argument
1919 #define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ argument
1940 #define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ argument
1944 #define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ argument
1962 #define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ argument
1966 #define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ argument
1987 #define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ argument
1991 #define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ argument
2039 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ argument
2043 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
2061 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ argument
2065 #define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
2083 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
2087 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
2111 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
2115 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
2133 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
2137 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
2161 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
2165 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
2183 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
2187 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
2205 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
2209 #define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
2230 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
2234 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
2252 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
2256 #define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
2277 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ argument
2281 #define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
2299 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
2303 #define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
2321 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ argument
2325 #define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ argument
2343 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ argument
2347 #define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ argument
2368 #define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ argument
2372 #define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ argument
2390 #define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ argument
2394 #define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ argument
2415 #define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ argument
2419 #define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ argument
2467 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ argument
2471 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ argument
2489 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ argument
2493 #define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ argument
2511 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ argument
2515 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ argument
2539 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ argument
2543 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ argument
2561 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ argument
2565 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ argument
2589 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ argument
2593 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ argument
2611 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ argument
2615 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ argument
2633 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ argument
2637 #define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ argument
2658 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
2662 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
2680 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
2684 #define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
2705 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ argument
2709 #define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
2727 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
2731 #define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
2749 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ argument
2753 #define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ argument
2771 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ argument
2775 #define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ argument
2796 #define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ argument
2800 #define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ argument
2821 #define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ argument
2825 #define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ argument
2846 #define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ argument
2850 #define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ argument
2901 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ argument
2905 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
2923 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ argument
2927 #define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
2945 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
2949 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
2973 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
2977 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
3001 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
3005 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
3023 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3027 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3045 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3049 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3070 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ argument
3074 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3092 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3096 #define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3114 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ argument
3118 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3136 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ argument
3140 #define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3161 #define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ argument
3165 #define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ argument
3186 #define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ argument
3190 #define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ argument
3211 #define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ argument
3215 #define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ argument
3266 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ argument
3270 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
3288 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ argument
3292 #define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
3310 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
3314 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
3338 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
3342 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
3366 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
3370 #define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
3388 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3392 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3410 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3414 #define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3435 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ argument
3439 #define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3457 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3461 #define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3479 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ argument
3483 #define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3501 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ argument
3505 #define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3526 #define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ argument
3530 #define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ argument
3551 #define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ argument
3555 #define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ argument
3576 #define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ argument
3580 #define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ argument
3631 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ argument
3635 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
3653 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ argument
3657 #define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
3675 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
3679 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
3703 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
3707 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
3731 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
3735 #define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
3753 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
3757 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
3775 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
3779 #define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
3800 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ argument
3804 #define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
3822 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
3826 #define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
3844 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ argument
3848 #define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ argument
3866 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ argument
3870 #define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ argument
3891 #define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ argument
3895 #define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ argument
3916 #define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ argument
3920 #define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ argument
3941 #define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ argument
3945 #define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ argument
3996 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4000 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4018 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4022 #define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4040 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4044 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4068 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4072 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4096 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4100 #define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4118 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4122 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4140 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4144 #define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4165 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ argument
4169 #define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4187 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4191 #define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4209 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ argument
4213 #define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4231 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ argument
4235 #define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4256 #define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ argument
4260 #define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ argument
4281 #define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ argument
4285 #define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ argument
4306 #define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ argument
4310 #define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ argument
4361 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4365 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4383 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4387 #define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4405 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4409 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4433 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4437 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4461 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4465 #define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4483 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4487 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4505 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4509 #define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4530 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ argument
4534 #define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4552 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4556 #define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4574 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ argument
4578 #define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4596 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ argument
4600 #define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4621 #define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ argument
4625 #define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ argument
4646 #define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ argument
4650 #define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ argument
4671 #define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ argument
4675 #define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ argument
4726 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ argument
4730 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
4748 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ argument
4752 #define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
4770 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
4774 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
4798 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
4802 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
4826 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
4830 #define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
4848 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
4852 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
4870 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
4874 #define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
4895 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ argument
4899 #define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
4917 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
4921 #define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
4939 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ argument
4943 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ argument
4961 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ argument
4965 #define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ argument
4986 #define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ argument
4990 #define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ argument
5011 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ argument
5015 #define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ argument
5036 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ argument
5040 #define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ argument
5091 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ argument
5095 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
5113 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ argument
5117 #define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
5135 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
5139 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
5163 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
5167 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
5191 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
5195 #define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
5213 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
5217 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
5235 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
5239 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
5260 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ argument
5264 #define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
5282 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
5286 #define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
5304 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ argument
5308 #define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ argument
5326 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ argument
5330 #define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ argument
5351 #define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ argument
5355 #define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ argument
5376 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ argument
5380 #define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ argument
5401 #define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ argument
5405 #define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ argument
5456 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ argument
5460 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ argument
5478 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ argument
5482 #define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ argument
5500 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ argument
5504 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ argument
5528 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ argument
5532 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ argument
5556 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ argument
5560 #define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ argument
5578 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ argument
5582 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ argument
5600 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ argument
5604 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ argument
5625 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ argument
5629 #define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ argument
5647 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ argument
5651 #define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ argument
5669 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ argument
5673 #define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ argument
5694 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ argument
5698 #define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ argument
5716 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ argument
5720 #define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ argument
5738 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ argument
5742 #define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ argument
5760 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ argument
5764 #define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ argument
5782 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ argument
5786 #define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ argument
5804 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ argument
5808 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ argument
5826 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ argument
5830 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ argument
5848 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ argument
5852 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ argument
5870 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ argument
5874 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ argument
5892 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ argument
5896 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ argument
5914 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ argument
5918 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ argument
5936 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ argument
5940 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ argument
5958 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ argument
5962 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ argument
5980 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ argument
5984 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ argument
6002 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ argument
6006 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ argument
6024 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ argument
6028 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ argument
6046 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ argument
6050 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ argument
6068 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ argument
6072 #define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ argument
6090 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ argument
6094 #define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ argument
6112 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ argument
6116 #define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ argument
6134 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ argument
6138 #define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ argument
6156 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ argument
6160 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ argument
6178 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ argument
6182 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ argument
6200 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ argument
6204 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ argument
6222 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ argument
6226 #define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ argument
6244 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ argument
6248 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ argument
6266 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ argument
6270 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ argument
6288 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ argument
6292 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ argument
6310 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ argument
6314 #define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ argument
6332 #define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ argument
6336 #define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ argument
6354 #define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ argument
6358 #define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ argument
6385 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ argument
6389 #define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ argument
6407 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ argument
6411 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ argument
6429 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ argument
6433 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ argument
6451 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ argument
6455 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ argument
6473 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ argument
6477 #define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ argument
6495 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ argument
6499 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ argument
6517 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ argument
6521 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ argument
6539 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ argument
6543 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ argument
6561 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ argument
6565 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ argument
6583 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ argument
6587 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ argument
6605 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ argument
6609 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ argument
6627 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ argument
6631 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ argument
6649 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ argument
6653 #define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ argument
6671 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ argument
6675 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ argument
6693 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ argument
6697 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ argument
6715 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ argument
6719 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ argument
6737 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ argument
6741 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ argument
6759 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ argument
6763 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ argument
6781 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ argument
6785 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ argument
6803 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ argument
6807 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ argument
6825 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ argument
6829 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ argument
6847 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ argument
6851 #define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ argument
6872 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ argument
6876 #define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ argument
6894 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ argument
6898 #define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ argument
6916 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ argument
6920 #define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ argument
6944 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ argument
6948 #define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
6966 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ argument
6970 #define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ argument
7024 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ argument
7028 #define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ argument
7055 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ argument
7059 #define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ argument
7083 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ argument
7087 #define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ argument
7114 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ argument
7118 #define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ argument
7145 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ argument
7149 #define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ argument
7194 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ argument
7198 #define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ argument
7219 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ argument
7223 #define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ argument
7241 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ argument
7245 #define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ argument
7266 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ argument
7270 #define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ argument
7294 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ argument
7298 #define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ argument
7322 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ argument
7326 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ argument
7344 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ argument
7348 #define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ argument
7366 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ argument
7370 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ argument
7388 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ argument
7392 #define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ argument
7410 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ argument
7414 #define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ argument
7441 #define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ argument
7445 #define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ argument
7490 #define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ argument
7494 #define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ argument
7515 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ argument
7519 #define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ argument
7537 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ argument
7541 #define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ argument
7559 #define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ argument
7563 #define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ argument
7608 #define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ argument
7612 #define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ argument
7630 #define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ argument
7634 #define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ argument
7652 #define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ argument
7656 #define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ argument
7674 #define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ argument
7678 #define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ argument
7696 #define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ argument
7700 #define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ argument
7730 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ argument
7734 #define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ argument
7755 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ argument
7759 #define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ argument
7786 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ argument
7790 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ argument
7808 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ argument
7812 #define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ argument
7830 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ argument
7834 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ argument
7852 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ argument
7856 #define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ argument
7874 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ argument
7878 #define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ argument
7896 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ argument
7900 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ argument
7921 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ argument
7925 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ argument
7946 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ argument
7950 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ argument
7971 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ argument
7975 #define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ argument
7996 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ argument
8000 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ argument
8018 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ argument
8022 #define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ argument
8040 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ argument
8044 #define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ argument
8065 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ argument
8069 #define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
8087 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \ argument
8091 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \ argument
8118 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \ argument
8122 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \ argument
8140 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \ argument
8144 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \ argument
8162 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \ argument
8166 #define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \ argument
8205 #define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ argument
8209 #define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ argument
8227 #define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ argument
8231 #define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ argument
8255 #define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ argument
8259 #define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ argument
8277 #define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ argument
8281 #define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ argument
8299 #define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ argument
8303 #define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ argument
8321 #define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ argument
8325 #define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ argument
8343 #define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ argument
8347 #define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ argument
8365 #define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ argument
8369 #define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ argument
8387 #define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ argument
8391 #define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ argument
8409 #define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ argument
8413 #define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ argument
8431 #define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ argument
8435 #define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ argument
8453 #define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ argument
8457 #define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ argument
8475 #define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ argument
8479 #define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ argument
8497 #define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ argument
8501 #define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ argument
8522 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ argument
8526 #define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ argument
8544 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ argument
8548 #define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ argument
8566 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ argument
8570 #define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ argument
8588 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ argument
8592 #define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ argument
8610 #define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ argument
8614 #define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ argument
8632 #define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ argument
8636 #define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ argument
8654 #define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ argument
8658 #define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ argument
8676 #define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ argument
8680 #define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ argument
8698 #define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ argument
8702 #define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ argument
8720 #define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ argument
8724 #define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ argument
8742 #define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ argument
8746 #define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ argument
8764 #define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ argument
8768 #define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ argument
8786 #define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ argument
8790 #define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ argument
8808 #define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ argument
8812 #define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ argument
8830 #define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ argument
8834 #define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ argument
8852 #define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ argument
8856 #define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ argument
8874 #define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ argument
8878 #define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ argument
8896 #define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ argument
8900 #define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ argument
8918 #define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ argument
8922 #define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ argument
8940 #define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ argument
8944 #define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ argument
8962 #define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ argument
8966 #define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ argument
8984 #define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ argument
8988 #define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ argument
9006 #define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ argument
9010 #define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ argument
9028 #define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ argument
9032 #define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ argument
9050 #define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ argument
9054 #define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ argument
9072 #define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ argument
9076 #define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ argument