platform/icnss2/main.h

215 struct icnss_stats {  struct
216 	struct {
219 	} events[ICNSS_DRIVER_EVENT_MAX];
221 	struct {
224 	} soc_wake_events[ICNSS_SOC_WAKE_EVENT_MAX];
226 	struct {
231 	} ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
233 	struct {
238 	} recovery;
240 	uint32_t pm_suspend;
241 	uint32_t pm_suspend_err;
242 	uint32_t pm_resume;
243 	uint32_t pm_resume_err;
244 	uint32_t pm_suspend_noirq;
245 	uint32_t pm_suspend_noirq_err;
246 	uint32_t pm_resume_noirq;
247 	uint32_t pm_resume_noirq_err;
248 	uint32_t pm_stay_awake;
249 	uint32_t pm_relax;
251 	uint32_t ind_register_req;
252 	uint32_t ind_register_resp;
253 	uint32_t ind_register_err;
254 	uint32_t msa_info_req;
255 	uint32_t msa_info_resp;
256 	uint32_t msa_info_err;
257 	uint32_t msa_ready_req;
258 	uint32_t msa_ready_resp;
259 	uint32_t msa_ready_err;
260 	uint32_t msa_ready_ind;
261 	uint32_t cap_req;
262 	uint32_t cap_resp;
263 	uint32_t cap_err;
264 	uint32_t pin_connect_result;
265 	uint32_t cfg_req;
266 	uint32_t cfg_resp;
267 	uint32_t cfg_req_err;
268 	uint32_t mode_req;
269 	uint32_t mode_resp;
270 	uint32_t mode_req_err;
271 	uint32_t ini_req;
272 	uint32_t ini_resp;
273 	uint32_t ini_req_err;
274 	u32 rejuvenate_ind;
275 	uint32_t rejuvenate_ack_req;
276 	uint32_t rejuvenate_ack_resp;
277 	uint32_t rejuvenate_ack_err;
278 	uint32_t device_info_req;
279 	uint32_t device_info_resp;
280 	uint32_t device_info_err;
281 	u32 exit_power_save_req;
282 	u32 exit_power_save_resp;
283 	u32 exit_power_save_err;
284 	u32 enter_power_save_req;
285 	u32 enter_power_save_resp;
286 	u32 enter_power_save_err;
287 	u32 soc_wake_req;
288 	u32 soc_wake_resp;
289 	u32 soc_wake_err;
290 	u32 restart_level_req;
291 	u32 restart_level_resp;
292 	u32 restart_level_err;